Double cipher hardware scheme for next generation ubiquitous communication and VLSI implementation
| Project/Area Number |
21500048
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hirosaki University |
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Principal Investigator |
FUKASE Masaaki 弘前大学, 大学院・理工学研究科, 教授 (10125643)
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| Co-Investigator(Kenkyū-buntansha) |
SATO Tomoaki 弘前大学, 総合情報処理センター, 准教授 (00336992)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2010: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
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| Keywords | ユビキタスプロセッサ / CMOS / チップ / ハードウェア暗号 / 二重化暗号 / 次世代IT / ユビキタス / VLSI / 暗号 / ハードウェア |
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| Research Abstract |
We have developed, in this study, a double cipher hardware scheme composed of RAC (random addressing cryptography) and hiding data. The cipher scheme has been implemented in a VLSI processor. The clock speed and power consumption of a 0.18-μm CMOS, 5.0 mm×7.5 mm chip are 200 MHz and 275 mW. The throughput and hardware cost of a cipher pipe is 0.19 GOPS and 0.1 mm square filled with 270 cells.
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Report
(4 results)
Research Products
(119 results)
