| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2010: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
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| Research Abstract |
We have developed, in this study, a double cipher hardware scheme composed of RAC (random addressing cryptography) and hiding data. The cipher scheme has been implemented in a VLSI processor. The clock speed and power consumption of a 0.18-μm CMOS, 5.0 mm×7.5 mm chip are 200 MHz and 275 mW. The throughput and hardware cost of a cipher pipe is 0.19 GOPS and 0.1 mm square filled with 270 cells.
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