Interconnect-centric LSI systems based on high-speed data transmission assisted by time-domain information processing

• Project/Area Number: 21500051
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Gunma University
• Principal Investigator: YUMINAKA Yasushi 群馬大学, 大学院・工学研究科, 准教授 (30272272)
• Project Period (FY): 2009 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2010: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2009: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
• Keywords: 集積回路 / VLSIシステム / 等化回路 / 多値情報処理 / 波形整形 / プリエンファシス / 高速インタフェース / 時間軸情報処理 / 時間領域信号処理 / パルス幅変調(PWM)

Research Abstract

The performance of recent high-speed VLSI systems is significantly limited by the interconnection bandwidth inside/between chips relative to individual transistor performance. The attenuation or deterioration of signals, arises from physical phenomena in transmission lines, limits achievable data rates and transmission distance. In this research, we have proposed following techniques to overcome the issues. (1)A new type of transmitter pre-emphasis technique based on pulse-width modulation (PWM) of a digitally coded signal. (2) An Efficient data coding scheme suited to channel characteristics and its application to wireless interconnection for 3D ICs.

Research Products

• [Journal Article] Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels (2012)
  • Author(s): Y. Yuminaka, K. Kawano
  • Journal Title: Journal of Multiple-Valued Logic and Soft Computing Volume: (In Press)
  • Peer Reviewed
• [Journal Article] A Dicode Signaling Scheme for Capacitively Coupled Interface (2012)
  • Author(s): Y. Yuminaka, K. Kawano
  • Journal Title: Key Engineering Materials Volume: Vol.497 Pages: 296-305
  • Peer Reviewed
• [Journal Article] High-Speed Multiple-Valued Data Transmission Based on Time-domain Pre-Emphasis Techniques (2011)
  • Author(s): Y. Yuminaka, K. Henmi
  • Journal Title: Key Engineering Materials Volume: Vol.459 Pages: 260-270
  • Peer Reviewed
• [Journal Article] High-Speed Data Transmission Techniques using Raised Cosine Signaling (2011)
  • Author(s): Y. Yuminaka
  • Journal Title: Key Engineering Materials Volume: Vol.459 Pages: 252-259
  • Peer Reviewed
• [Journal Article] High-speed data transmission techniques using raised cosine signaling (2011)
  • Author(s): Y.Yuminaka
  • Journal Title: Key Engineering Materials Volume: 459 Pages: 252-259
  • Peer Reviewed
• [Journal Article] High-speed multiple-valued data transmission based on time-domain pre-emphasis techniques (2011)
  • Author(s): Y.Yuminaka, K.Henmi
  • Journal Title: Key Engineering Materials Volume: 459 Pages: 260-270
  • Peer Reviewed
• [Journal Article] Multiple-Valued Data Transmission based on Time-Domain Pre-Emphasis Techniques (2010)
  • Author(s): Y. Yuminaka, Y. Takahashi, K. Henmi
  • Journal Title: IEICE Trans. on Information and Systems Volume: Vol.E93-D,No.8 Pages: 2109-2116
  • NAID: 10027364590
  • Peer Reviewed
• [Journal Article] Multiple-valued data transmission based on time-domainpre-emphasis techniques (2010)
  • Author(s): Y.Yuminaka, Y.Takahashi, K.Henmi
  • Journal Title: IEICE Trans. on Information and Systems Volume: E93-D Pages: 2109-2116
  • Peer Reviewed
• [Journal Article] Time-Domain Pre-Emphasis Techniques for Multiple-Valued Data Transmission (2009)
  • Author(s): Y. Yuminaka, Y. Takahashi
  • Journal Title: Journal of Multiple-Valued Logic and Soft Computing Volume: Vol.15 Pages: 301-313
  • Peer Reviewed
• [Journal Article] Multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects (2009)
  • Author(s): Y.Yuminaka, Y.Takahashi, K.Henmi
  • Journal Title: IEEE Proc.39th Int.Symp.Multiple-Valued Logic 39 Pages: 250-255
  • Peer Reviewed
• [Journal Article] Time-domain pre-emphasis techniques for multiple-valued data transmission (2009)
  • Author(s): Y.Yuminaka, Y.Takahashi
  • Journal Title: Journal of Multiple-Valued Logic and Soft Computing 15 Pages: 301-313
  • Peer Reviewed
• [Journal Article] High-speed multiple-valued data transmission based on time-domain pre-emphasis techniques (2009)
  • Author(s): Y.Yuminaka, Y.Takahashi, K.Henmi
  • Journal Title: International Conference on Advanced Micro-Device Engineering(AMDE) 1
  • Peer Reviewed
• [Presentation] Efficient Data Transmission using Multiple-Valued Pulse-Position Modulation (2012)
  • Author(s): Y. Yuminaka, M. Okui
  • Organizer: IEEE Proc. 42nd Int. Symp. Multiple-Valued Logic
  • Place of Presentation: (Accept) Victoria BC (Canada)
  • Year and Date: 2012-05-14
• [Presentation] Experimental FPGA Implementation of 2nd-Order Time-Domain Pre-Emphasis Techniques (2011)
  • Author(s): Y. Yuminaka, S. Ishida, K. Henmi
  • Organizer: International Conference on Advanced Micro-Device Engineering
  • Place of Presentation: Kiryu
  • Year and Date: 2011-12-08
• [Presentation] Experimental FPGA Implementation of 2nd-Order Time-Domain Pre-Emphasis Techniques (2011)
  • Author(s): Y.Yuminaka, S.Ishida, K.Henmi
  • Organizer: 3rd International Conference on Advanced Micro-Device Engineering
  • Place of Presentation: 桐生市市民文化会館(群馬)
  • Year and Date: 2011-12-08
• [Presentation] 多値パルス位置変調を用いた2次元情報表現に基づく高速信号伝送方式 (2011)
  • Author(s): 奥井正明, 弓仲康史
  • Organizer: 第34回多値論理Forum
  • Place of Presentation: つくば
  • Year and Date: 2011-09-17
• [Presentation] 多値パルス位置変調を用いた2次元情報表現に基づく高速信号伝送方式 (2011)
  • Author(s): 奥井正明, 弓仲康史
  • Organizer: 第34回多値論理Forum
  • Place of Presentation: つくば研究支援センター(茨城)
  • Year and Date: 2011-09-17
• [Presentation] A 2nd-Order Time-Domain Pre-Emphasis Technique and Its Experimental FPGA Implementation (2011)
  • Author(s): Y. Yuminaka, S. Ishida, K. Henmi
  • Organizer: 20th International Workshop on Post-Binary ULSI Systems
  • Place of Presentation: Tuusula(Finland)
  • Year and Date: 2011-05-22
• [Presentation] A 2nd-Order Time-Domain Pre-Emphasis Technique and Its Experimental FPGA Implementation (2011)
  • Author(s): Y.Yuminaka, S.Ishida, K.Henmi
  • Organizer: 20th International Workshop on Post-Binary ULSI Systems
  • Place of Presentation: Tuusula(フィンランド)
  • Year and Date: 2011-05-22
• [Presentation] Partial-Response Signaling Scheme for High-Speed Data Transmission (2010)
  • Author(s): Y. Yuminaka, K. Kawano
  • Organizer: International Conference on Advanced Micro-Device Engineering
  • Place of Presentation: Kiryu
  • Year and Date: 2010-12-10
• [Presentation] Partial-response signaling scheme for high-speed data transmission (2010)
  • Author(s): Y.Yuminaka, K.Kawano
  • Organizer: International Conference on Advanced Micro-Device Engineering
  • Place of Presentation: 桐生
  • Year and Date: 2010-12-10
• [Presentation] Data-Dependent Time-Domain Pre-Emphasis Techniques for High-Speed Data Transmission (2010)
  • Author(s): Y. Yuminaka, K. Henmi
  • Organizer: IEEE Int. Symp. on Communications and Information Technologies 2010
  • Place of Presentation: Tokyo
  • Year and Date: 2010-10-29
• [Presentation] Data-dependent time-domain pre-emphasis techniques for high-speed data transmission (2010)
  • Author(s): Y.Yuminaka, K.Henmi
  • Organizer: IEEE Int.Symp.on Communications and Information Technologies 2010
  • Place of Presentation: 東京
  • Year and Date: 2010-10-29
• [Presentation] A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface (2010)
  • Author(s): Y. Yuminaka, K. Kawano
  • Organizer: IEEE Proc. 40th Int. Symp. Multiple-Valued Logic
  • Place of Presentation: Barcelona(USA)
  • Year and Date: 2010-05-27
• [Presentation] A ternary partial-response signaling scheme for capacitively coupled interface (2010)
  • Author(s): Y.Yuminaka, K.Kawano
  • Organizer: IEEE Proc.40th Int.Symp.Multiple-Valued Logic
  • Place of Presentation: バルセロナ(スペイン)
  • Year and Date: 2010-05-27
• [Presentation] パルス幅変調プリエンファシスを用いた高速多値信号伝送技術 (2010)
  • Author(s): 逸見憲一, 弓仲康史
  • Organizer: 電気学会電子回路研究会
  • Place of Presentation: 桐生
  • Year and Date: 2010-03-25
• [Presentation] パルス幅変調プリエンファシスを用いた高速多値信号伝送技術 (2010)
  • Author(s): 逸見憲一、弓仲康史
  • Organizer: 電気学会電子回路研究会
  • Place of Presentation: 群馬大学工学部(桐生)
  • Year and Date: 2010-03-25
• [Presentation] High-Speed Multiple-Valued Data Transmission Based on Time-domain Pre-Emphasis Techniques (2009)
  • Author(s): Y. Yuminaka, Y. Takahashi, K. Henmi
  • Organizer: International Conference on Advanced Micro-Device Engineering
  • Place of Presentation: Kiryu
  • Year and Date: 2009-12-11
• [Presentation] Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques in Consideration of Higher-order Channel Effects (2009)
  • Author(s): Y. Yuminaka, Y. Takahashi, K. Henmi
  • Organizer: IEEE Proc. 39th Int. Symp. Multiple-Valued Logic
  • Place of Presentation: Naha
  • Year and Date: 2009-05-23
• [Remarks]
  • URL: http://cs3.el.gunma-u.ac.jp
• [Remarks]
  • URL: http://cs3.el.gunma-u.ac.jp
• [Remarks]
  • URL: http://cs3.el.gunma-u.ac.jp
• [Remarks]
  • URL: http://cs3.el.gunma-u.ac.jp