Development of New Generation Readout System for the ATLAS Muon System Based on High Performance Advanced Logic Devices
| Project/Area Number |
21540296
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Particle/Nuclear/Cosmic ray/Astro physics
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| Research Institution | The University of Tokyo |
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Principal Investigator |
SAKAMOTO Hiroshi 東京大学, 素粒子物理国際研究センター, 教授 (80178574)
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| Co-Investigator(Kenkyū-buntansha) |
KAWAMOTO Tatsuo 東京大学, 素粒子物理国際研究センター, 准教授 (80153021)
ISHINO Masaya 東京大学, 素粒子物理国際研究センター, 助教 (30334238)
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| Co-Investigator(Renkei-kenkyūsha) |
SASAKI Osamu 高エネルギー加速器研究機構, 素粒子原子核研究所, 教授 (30178636)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2011: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2010: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2009: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | 素粒子実験 / 陽子陽子衝突 / データ収集 / FPGA / CPUコア / 高速データ通信 / LHC加速器 / アトラス実験 / データ収集系 / 高速シリアル通信 / ハードウエア記述言語 / 陽子陽子衝突実験 / ミューオン検出器 / データ読み出し系 / 高速シリアル伝送 / データ圧縮 / エラーリカバリー |
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| Research Abstract |
Technical evaluation is performed on recent high performance login devices, especially on FPGAs. A general purpose logic module in the VME standard is developed by using a typical device. By using it, high speed serial communication, connecting between such devices, is tested. Furthermore, a software CPU core, which uses normal logic blocks of FPGAs, is evaluated. Finally, the design and its verification of the new readout system for the foreseen upgrade of the end-cap muon trigger system is done.
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Report
(4 results)
Research Products
(10 results)
