Study on automatic operating margin maximization for analog VLSI circuits with the endurance for device characteristic variation and aging degradation.

• Project/Area Number: 21560356
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: NAKAMURA Kazuyuki 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
• Project Period (FY): 2009 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2009: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
• Keywords: CMOS / アナログ回路 / 素子劣化 / ばらつき / 最適化 / 環境変化 / 動作マージン / 経年劣化 / 環境変動

Research Abstract

A new design method : “automatic operating margin maximization method“ was developed to achieve the high reliable LSIs for the automotive / robot with avoiding the problems of environmental (temperature) changes, variations, aging, etc.. For oscillators, analog amplifier, and memory (SRAM) circuits, the margin maximization technique, performance tuning technique and advanced margin-free design concept were developed respectively. Two papers, four international conference talks and two patents was issued.

Research Products

• [Journal Article] Complementary Metal Oxide Semiconductor Operational Amplifier Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String Digital-to-Analog Converter (2012)
  • Author(s): Hiroyuki Morimoto, Hiroaki Goto, Hajime Fujiwara, Kazuyuki Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: Vol.51 No.2 Issue: 2S Pages: 02BE10-02BE10
  • DOI: 10.1143/jjap.51.02be10
  • NAID: 120006782184
  • Peer Reviewed
• [Journal Article] An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O (2011)
  • Author(s): H. Morimoto, H. Koike, K. Nakamura
  • Journal Title: IEICE Transactions on Electronics Volume: E94-C Issue: 6 Pages: 945-952
  • DOI: 10.1587/transele.E94.C.945
  • NAID: 10029804120
  • ISSN: 0916-8524, 1745-1353
  • Peer Reviewed
• [Journal Article] An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches (2010)
  • Author(s): Y. Kohara, M. Asano, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: Vol. 49, Issue 4
  • NAID: 120006782186
  • Peer Reviewed
• [Journal Article] An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches (2010)
  • Author(s): Yusuke Kohara, Masaharu Asano, Yoshihiro Kawakami, Yasuhisa Uchida, Hiroki Koike, Kazuyuki Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: Volume 49, Issue 4
  • NAID: 120006782186
  • Peer Reviewed
• [Presentation] A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM (2012)
  • Author(s): T. Saito, H. Okamura, M. Yamamoto, K. Nakamura
  • Organizer: 2012 4th IEEE International Memory Workshop (IMW)
  • Place of Presentation: Milano Italy
  • Year and Date: 2012-05-29
• [Presentation] A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch (2012)
  • Author(s): Y. Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura
  • Organizer: IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012
  • Place of Presentation: San Diego USA
  • Year and Date: 2012-03-20
• [Presentation] A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch (2012)
  • Author(s): Y.Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura
  • Organizer: IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012
  • Place of Presentation: San Diego, USA
• [Presentation] A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM (2012)
  • Author(s): Saito, T. ; Okamura, H. ; Yamamoto, H. ;
  • Organizer: 2012 4th IEEE International Memory Workshop (IMW)
  • Place of Presentation: Milan, Italy
• [Presentation] 省面積抵抗ストリング DAC と閉ループ・オフセット検出を用いた CMOS オペアンプのオフセット校正 (2011)
  • Author(s): 森本浩之、後藤弘明、藤原宗、中村
  • Organizer: デザインガイア 2011
  • Place of Presentation: 宮崎市
  • Year and Date: 2011-11-28
• [Presentation] An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch (2011)
  • Author(s): Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura
  • Organizer: 2011 International Conference on Solid State Devices and Materials(SSDM)
  • Place of Presentation: Nagoya Japan
  • Year and Date: 2011-09-29
• [Presentation] CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC (2011)
  • Author(s): H. Morimoto, H. Goto, H. Fujiwara, K. Nakamura
  • Organizer: 2011 International Conference on Solid State Devices and Materials(SSDM)
  • Place of Presentation: Nagoya Japan
  • Year and Date: 2011-09-29
• [Presentation] CMOS偶数段リング発振回路の設計マージンの測定 (2011)
  • Author(s): 平川豊・本村綾美・三村法寛・中村和之
  • Organizer: 電子情報通信学会 2011総合大会
  • Place of Presentation: 東京都市大学
  • Year and Date: 2011-03-16
• [Presentation] 電源遷移時間を考慮した偶数段リング発振回路発振領域の検討 (2011)
  • Author(s): 三村、平川、中村
  • Organizer: 電子情報通信学会 2011 総合大会
  • Place of Presentation: 東京
  • Year and Date: 2011-03-15
• [Presentation] CMOS偶数段リング発振回路の設計マージンの測定 (2011)
  • Author(s): 平川、本村、三村、中村
  • Organizer: 電子情報通信学会 2011 総合大会
  • Place of Presentation: 東京
  • Year and Date: 2011-03-15
• [Presentation] 電源遷移時間を考慮した偶数段リング発振回路発振領域の検討 (2011)
  • Author(s): 三村法寛・平川豊・中村和之
  • Organizer: 電子情報通信学会 2011総合大会
  • Place of Presentation: 東京都市大学
  • Year and Date: 2011-03-15
• [Presentation] CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC (2011)
  • Author(s): H. Morimoto, H. Koike, K. Nakamura
  • Organizer: 2011 International Conference on Solid State Devices and Materials(SSDM)
  • Place of Presentation: Nagoya, Japan
• [Presentation] An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch (2011)
  • Author(s): Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura
  • Organizer: International Conference on Solid State Devices and Materials(SSDM)
  • Place of Presentation: Nagoya, Japan
• [Presentation] 複数個のラッチを有する CMOS 偶数段リング発振回路の最適設計 (2010)
  • Author(s): 平川、小原、川上、中村
  • Organizer: LSI とシステムのワークショップ 2010
  • Place of Presentation: 北九州市
  • Year and Date: 2010-05-18
• [Presentation] 複数個のラッチを有するCMOS偶数段リング発振回路の最適設計 (2010)
  • Author(s): 平川豊, 小原祐輔, 川上義弘, 中村和之
  • Organizer: LSIとシステムのワークショップ2010
  • Place of Presentation: 北九州国際会議場
  • Year and Date: 2010-05-18
• [Presentation] 片チャネルラッチ構成の偶数段リング発振回路の検討 (2010)
  • Author(s): 小原、平川、中村
  • Organizer: 電子情報通信学会 2010 総合大会
  • Place of Presentation: 仙台市
  • Year and Date: 2010-03-16
• [Presentation] 片チャネルラッチ構成の偶数段リング発振回路の検討 (2010)
  • Author(s): 小原祐輔、平川豊、中村和之
  • Organizer: 電子情報通信学会2010総合大会
  • Place of Presentation: 東北大学
  • Year and Date: 2010-03-16
• [Patent(Industrial Property Rights)] 半導体記憶装置 (2012)
  • Inventor(s): 中村和之、齋藤貴彦、岡村均
  • Industrial Property Rights Holder: 九州工業大学
  • Industrial Property Number: 2012-076414
  • Filing Date: 2012-03-29
• [Patent(Industrial Property Rights)] 半導体記憶装置 (2011)
  • Inventor(s): 中村和之、齋藤貴彦
  • Industrial Property Rights Holder: 九州工業大学
  • Industrial Property Number: 2011-035109
  • Filing Date: 2011-02-21