Study on automatic operating margin maximization for analog VLSI circuits with the endurance for device characteristic variation and aging degradation.
| Project/Area Number |
21560356
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Kyushu Institute of Technology |
|---|
Principal Investigator |
NAKAMURA Kazuyuki 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
|
|---|
| Project Period (FY) |
2009 – 2011
|
| Project Status |
Completed (Fiscal Year 2011)
|
| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
|
|---|
| Keywords | CMOS / アナログ回路 / 素子劣化 / ばらつき / 最適化 / 環境変化 / 動作マージン / 経年劣化 / 環境変動 |
|---|
| Research Abstract |
A new design method : “automatic operating margin maximization method“ was developed to achieve the high reliable LSIs for the automotive / robot with avoiding the problems of environmental (temperature) changes, variations, aging, etc.. For oscillators, analog amplifier, and memory (SRAM) circuits, the margin maximization technique, performance tuning technique and advanced margin-free design concept were developed respectively. Two papers, four international conference talks and two patents was issued.
|
Report
(4 results)
Research Products
(23 results)
