| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2013: ¥390,000 (Direct Cost: ¥300,000、Indirect Cost: ¥90,000)
Fiscal Year 2012: ¥390,000 (Direct Cost: ¥300,000、Indirect Cost: ¥90,000)
Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2010: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Research Abstract |
Single event tolerant spaceborne LSI circuits have been designed by embedding cascade voltage switch logic (CVSL) circuits, high-speed gates, and neuron MOS structures.
Single event transient (SET) effects on CVSL circuits have been investigated using SPICE. Static CVSL and clocked CVSL (C2VSL) circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. A CVSL half adder, a C2VSL half adder and a C2VSL full adder have confirmed to function correctly by the chip measurements. SET simulation results have confirmed that the CVSL and C2VSL circuits have increased tolerance to SET. SET tolerance for the CVSL and C2VSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL and C2VSL circuits are candidates for a SET tolerant spaceborne circuit. CVSL circuits are more than 200 times harder and C2VSL circuits are ten times harder than conventional CMOS circuits.
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