| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2010: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
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| Research Abstract |
FPGAs attract much attention since their functions and interconnection network can be reconfigured by post-fabrication programming. However, their major problem is its large area and power consumption because of their high redundancy. In this research, we develop novel architecture that can control the supply voltage and threshold voltage of each look-up table so as to minimize the power consumption under the constraint of the processing time. Moreover, we develop architecture that can gate the power when LUTs do not work.
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