Low-Power FPGA Based on Fine-grained Autonomous Supply-Voltage Control
Project/Area Number |
21700052
|
Research Category |
Grant-in-Aid for Young Scientists (B)
|
Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
|
Research Institution | Tohoku University |
Principal Investigator |
|
Project Period (FY) |
2009 – 2011
|
Project Status |
Completed (Fiscal Year 2011)
|
Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2010: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
|
Keywords | FPGA / 非同期式回路 / 不揮発メモリ / 複数電源電圧 / パワーゲーティング / 強誘電体 / フローティングゲートMOS / リーク電流 / 非同期回路 / ウェーブパイプライン / 強誘電体メモリ |
Research Abstract |
FPGAs attract much attention since their functions and interconnection network can be reconfigured by post-fabrication programming. However, their major problem is its large area and power consumption because of their high redundancy. In this research, we develop novel architecture that can control the supply voltage and threshold voltage of each look-up table so as to minimize the power consumption under the constraint of the processing time. Moreover, we develop architecture that can gate the power when LUTs do not work.
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Report
(4 results)
Research Products
(24 results)