| Project/Area Number |
21700057
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Toyohashi University of Technology |
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Principal Investigator |
KOBAYASHI Ryotaro Toyohashi University of Technology, 大学院・工学研究科, 講師 (40324454)
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| Project Period (FY) |
2009 – 2010
|
| Project Status |
Completed (Fiscal Year 2010)
|
| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2010: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2009: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | 計算機アーキテクチャ / メニーコア / マルチコア / ルータ / 記憶階層 / 予測 / コア融合 / メインメモリアクセス |
|---|
| Research Abstract |
Many core that facilitates some hundreds cores will be realized in the near future. Meanwhile, the hurdles that processors are faced with are becoming more diverse and severe. We study architectural techniques for many cores to cooperate and supply multi functions. We propose and evaluate dependable mechanism, dynamic core fusion mechanism, dynamic cache policy switching, and effective value prediction mechanism.
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