| Budget Amount *help |
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
|
|---|
| Research Abstract |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Although nondeterministic algorithms such as SA(Simulated Annealing) algorithm are successful in solving this problem, they are known to be slow. We have been introduced neural network approach which is a Kohonen SOM(Sefl Organizing feature Maps) to FPGA placement. In our method, it is important to represent the features of netlists. However, it is not enough to sufficient for using only connection matrix as a input vectors in terms of computational resources and time. In this paper, we proposed input vector based on a shimbel index. We also discuss three graph distance measurement to enhance placement quality. Our method can improve computational time compared with SA based VPR using some benchmark circuits in the evaluation.
|
