| Budget Amount *help |
¥18,460,000 (Direct Cost: ¥14,200,000、Indirect Cost: ¥4,260,000)
Fiscal Year 2012: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2011: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2010: ¥9,100,000 (Direct Cost: ¥7,000,000、Indirect Cost: ¥2,100,000)
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| Research Abstract |
We have investigated on a design method that achieves robust circuit operation under low supply voltage of around 0.7 V. In particular, we have worked onthree topics:
(1) built-in self monitor and compensation of die-to-die variation
(2) sequential logic gates tolerating for within-die variation
(3) evaluation of dynamic performance variation under low supply voltage.
We have successfully developed variation-tolerant D-FFs, all-digital monitors and body-bias generator circuits for performance compensation, and accurate evaluation of delay fluctuation due to Random Telegraph Noise.
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