Improving Hardware Verification Efficiency by Fusion of Formal Methods and Simulation
| Project/Area Number |
22500047
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Shimane University (2012)
Osaka University (2010-2011) |
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Principal Investigator |
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| Project Period (FY) |
2010 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2012: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | 設計検証技術 / フォーマル検証 / シミュレーションベース検証 / SAT ソルバ / SATソルバ / 有界モデル検査 / カバレッジ駆動検証 / 制約付きランダムパタン生成 / アサーションベース検証 |
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| Research Abstract |
Formal methods and simulation-based methods have been used for hardware verification in practical industrial designs. How to combine these two methods, however, has not been studied extensively yet. In this research, in terms of qualita tive verification metrics, we show effectiveness of our new approach, in which based on the results of simulation runs, a formal method is applied for improving the coverage metrics. We also show some experimental results, in which for a block module of se veral thousands of gates, the proposed method is effective.
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Report
(4 results)
Research Products
(3 results)
