A Hardware Acceleration of Evaluation Function for Shogi

• Project/Area Number: 22500118
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Intelligent informatics
• Research Institution: University of Tsukuba
• Principal Investigator: TOMIYASU Hiroshi 筑波大学, システム情報系, 講師 (50284550)
• Project Period (FY): 2010 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000); Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2010: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
• Keywords: 計算機システム / アーキテクチャ / 知能機械 / 探索問題 / アルゴリズム / ハードウェア化 / FPGA応用 / 情報工学 / 計算機アーキテクチャ / 電子デバイス・機器

Research Abstract

The goal of this theme is accelerating evaluation function of shogi with hardware. Calculating in parallel the evaluation function provides sufficient speed up. However, since throughput of producing following possible move with software is not sufficient, it can not utilize the speed of the evaluation function. Thus it is considered to be generated possible move for each cycle with hardware, but there is a difficulty in the detection of the repetition of moves. I am validating a hardware algorithm which can solve this detection problem.