Behavioral Synthesis Technology for FPGAs

• Project/Area Number: 22700050
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Ritsumeikan University
• Principal Investigator: TOMIYAMA Hiroyuki 立命館大学, 理工学部, 教授 (80362292)
• Project Period (FY): 2010 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000); Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2010: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
• Keywords: 動作合成 / 設計自動化 / FPGA / システムオンチップ

Research Abstract

We have developed behavioral synthesis technologies for Field-Programmable Gate Arrays(FPGSs). Our work minimizes the delay of multiplexers on critical paths through optimal allocation and binding of registers and functional resources. We have achieved approximately 10% performance improvement against a state-of-the-art technique.

Research Products

• [Journal Article] A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs (2012)
  • Author(s): K. Jozwik、H. Tomiyama、S. Honda、H. Takada
  • Journal Title: IEICE Transactions on Information and Systems Volume: E95-D Pages: 345-353
  • NAID: 10030610564
  • Peer Reviewed
• [Journal Article] A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs (2012)
  • Author(s): Krzysztof Jozwik
  • Journal Title: IEICE Transactions on Information and Systems Volume: E95-D Issue: 2 Pages: 345-353
  • DOI: 10.1587/transinf.E95.D.345
  • NAID: 10030610564
  • ISSN: 0916-8532, 1745-1361
  • Peer Reviewed
• [Journal Article] Comparison of Preemption Schemes for Partially Reconfigurable FPGAs
  • Author(s): K. Jozwik、H. Tomiyama、M. Edahiro, S. Honda、H. Takada
  • Journal Title: IEEE Embedded Systems Letters Volume: (印刷中)
  • Peer Reviewed
• [Journal Article] Comparison of Preemption Schemes for Partially Reconfigurable FPGAs
  • Author(s): Krzysztof Jozwik
  • Journal Title: IEEE Embedded Systems Letters Volume: (印刷中)(未定)
  • Peer Reviewed
• [Presentation] High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement (2012)
  • Author(s): Y. Hara-Azumi
  • Organizer: Workshop on Synthesis and System Integration of Mixed Information Technologies
  • Place of Presentation: 別府国際コンベンションセンター(大分県)
  • Year and Date: 2012-03-09
• [Presentation] Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis (2012)
  • Author(s): Y. Hara-Azumi
  • Organizer: Asia and South Pacific Design Automation Conference
  • Place of Presentation: シドニー(オーストラリア)
  • Year and Date: 2012-02-01
• [Presentation] Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis (2012)
  • Author(s): Y. Hara-Azumi
  • Organizer: International Conference on Embedded Software and Systems
  • Place of Presentation: リバプール(イギリス)
• [Presentation] Rainbow : An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs (2011)
  • Author(s): K. Jozwik
  • Organizer: International Conference on ReConFigurable Computing and FPGAs
  • Place of Presentation: カンクーン(メキシコ)
  • Year and Date: 2011-11-30
• [Presentation] Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems (2011)
  • Author(s): K. Jozwik
  • Organizer: International SoC Design Conference
  • Place of Presentation: 済州島(韓国)
  • Year and Date: 2011-11-18
• [Presentation] Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems (2011)
  • Author(s): Krzysztof Jozwik
  • Organizer: International SoC Design Conference
  • Place of Presentation: 済州島(韓国)(招待講演)
  • Year and Date: 2011-11-18
• [Presentation] Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers (2011)
  • Author(s): Krzysztof Jozwik
  • Organizer: 電子情報通信学会RECONF研究会
  • Place of Presentation: 名古屋大学(愛知県)
  • Year and Date: 2011-09-26
• [Presentation] Soft Error-Aware Scheduling in High-Level Synthesis (2011)
  • Author(s): Yuko Hara-Azumi
  • Organizer: 情報処理学会SLDM研究会
  • Place of Presentation: (開催中止(予稿集のみ発行))
  • Year and Date: 2011-03-18
• [Presentation] Simultaneous Allocation and Binding Considering Multiplexers in High-Level Synthesis (2011)
  • Author(s): Yuko Hara-Azumi
  • Organizer: 情報処理学会SLDM研究会
  • Place of Presentation: 慶應大学(神奈川県横浜市)
  • Year and Date: 2011-01-17
• [Presentation] Towards Practical High-Level Synthesis From Large Behavioral Descriptions (2010)
  • Author(s): Y. Hara-Azumi
  • Organizer: International SoC Design Conference
  • Place of Presentation: インチョン(韓国)
  • Year and Date: 2010-11-22
• [Presentation] Towards Practical High-Level Synthesis From Large Behavioral Descriptions (2010)
  • Author(s): Yuko Hara-Azumi
  • Organizer: International SoC Design Conference (ISOCC)
  • Place of Presentation: Inchon, Korea
  • Year and Date: 2010-11-22
• [Presentation] Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis (2010)
  • Author(s): Y. Hara-Azumi
  • Organizer: Workshop on Synthesis and System Integration of Mixed Information Technologies
  • Place of Presentation: 台北(台湾)
  • Year and Date: 2010-10-18
• [Presentation] Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis (2010)
  • Author(s): Yuko Hara-Azumi
  • Organizer: Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
  • Place of Presentation: Taipei, Taiwan
  • Year and Date: 2010-10-18
• [Presentation] A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems (2010)
  • Author(s): K. Jozwik
  • Organizer: International Conference on Field Programmable Logic and Applications
  • Place of Presentation: ミラノ(イタリア)
  • Year and Date: 2010-09-01
• [Presentation] A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems (2010)
  • Author(s): Krzysztof Jozwik
  • Organizer: International Conference on Field Programmable Logic and Applications (FPL)
  • Place of Presentation: Milano, Italy
  • Year and Date: 2010-09-01
• [Remarks]
  • URL: http://research-db.ritsumei.ac.jp/Profiles/81/0008041/profile.html
• [Remarks]
  • URL: http://www-ja.tomiyama-lab.org/publications
• [Remarks]
  • URL: http://research-db.ritsumei.ac.jp/Profiles/81/0008041/profile.html
• [Remarks]
  • URL: http://www-ja.tomiyama-lab.org/publications
• [Remarks]
  • URL: http://research-db.ritsumei.ac.jp/Profiles/81/0008041/profile.html
• [Remarks]
  • URL: http://www-ja.tomiyama-lab.org/publications