On-hip communication architecture for embedded multi-ore CPUs
Project/Area Number |
22700051
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Research Category |
Grant-in-Aid for Young Scientists (B)
|
Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
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Research Institution | Kyushu University (2011) Toyohashi University of Technology (2010) |
Principal Investigator |
SUGIHARA Makoto 九州大学, システムLSI研究センター, 准教授 (80373538)
|
Project Period (FY) |
2010 – 2011
|
Project Status |
Completed (Fiscal Year 2011)
|
Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2011: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
|
Keywords | オンチップ通信 / ネットワークオンチップ / 組込みシステム / 通信アーキテクチャ合成 / チップ面積 / 通信スループット / 通信レイテンシ / 階層バス / 設計自動化 / システムオンチップ / 通信アーキテクチャ / バス / ブリッジ / 自動合成 |
Research Abstract |
It is essential to satisfy the design requirements regarding chip area, performance, and energy consumption by optimizing a group of IP cores including CPU cores and its network when one utilizes multi-core CPUs as a component of application specific systems. It is important to build an EDA approach to automatically synthesize a communication mechanism as the number of transistors for a system is ever-increasing and the complexity of a system is increasing. In this work, we study a design methodology to synthesize on-chip communication architecture whose chip area, performance, and power consumption are optimized.
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Report
(3 results)
Research Products
(7 results)