Development of high-performance and low-power consumption many-core microprocessors using nonvolatile memory elements

• Project/Area Number: 22760248
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Electron device/Electronic equipment
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: YAMAMOTO Syuuichirou 東京工業大学, 大学院・総合理工学研究科, 助教 (50313375)
• Project Period (FY): 2010 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000); Fiscal Year 2012: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2010: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
• Keywords: メニーコアプロセッサ / 不揮発性メモリ / 低消費電力 / 強磁性トンネル接合 / パワーゲーティング / 電力削減効率

Research Abstract

In this study, aiming to develop new generation high-performance and low-power microprocessors by combination of parallel processing using a many-core processor technology and ideal power-gating (PG) technology using nonvolatile memories, the better circuit configuration was presented by developing an evaluation method of power reduction efficiency during power-gating. The total power reduction effect simultaneously using dynamic voltage-frequency scaling (DVFS) and PG technology was also verified through a simulation.

Research Products

• [Journal Article] Nonvolatile power-gating FPGA based on pseudo-spin-transistor architecture with spin-transfer-torque MTJs (2012)
  • Author(s): Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
  • Journal Title: MRS Symposium Proceedings Volume: Vol.1430 Pages: 55-60
  • DOI: 10.1557/opl.2012.1183
  • Peer Reviewed
• [Journal Article] Nonvolatile power-gating field-programmable gate array using nonvolatile static random access memory and nonvolatile delay flip-flops based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (2012)
  • Author(s): Shuu'ichirou Yamamoto, Yusuke Shuto,Satoshi Sugahara
  • Journal Title: Japanese Journal of Applied Physics Volume: Vol.51 Issue: 11S Pages: 11PB02-11PB02
  • DOI: 10.1143/jjap.51.11pb02
  • Peer Reviewed
• [Journal Article] Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems (2011)
  • Author(s): Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
  • Journal Title: Electronics Letters Volume: Vol.47 Issue: 18 Pages: 1027-1028
  • DOI: 10.1049/el.2011.1807
  • Peer Reviewed
• [Journal Article] CMOS/スピントロニクス融合技術による不揮発性ロジックシステムの展望 (2011)
  • Author(s): 菅原聡、周藤悠介、山本修一郎
  • Journal Title: まぐね Volume: 6巻 Pages: 5-15
  • NAID: 10027851011
• [Journal Article] Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems (2011)
  • Author(s): S.Yamamoto, Y.Shuto, S.Sugahara
  • Journal Title: Electronics Letters Volume: 47 Pages: 1027-1028
  • Peer Reviewed
• [Presentation] 疑似スピンMOSFETを用いた不揮発性デュアルポートSRAMセルの提案とNVPG応用 (2013)
  • Author(s): 山本修一郎
  • Organizer: 第60回応用物理学関係連合講演会
  • Place of Presentation: 神奈川工科大学、神奈川県
  • Year and Date: 2013-03-28
• [Presentation] Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications, IEEE International Semiconductor (2012)
  • Author(s): Shuu'ichirou Yamamoto
  • Organizer: Conference Dresden-Grenoble
  • Place of Presentation: Minatech Campus, Grenoble, France
  • Year and Date: 2012-09-25
• [Presentation] 疑似スピンMOSFET技術を用いたFPGAの不揮発性パワーゲーティング (2012)
  • Author(s): 山本修一郎
  • Organizer: 第73回応用物理学会学術講演会
  • Place of Presentation: 愛媛大学、愛媛県
  • Year and Date: 2012-09-13
• [Presentation] 疑似スピンMOSFETを用いた不揮発性DFF:BETにおける静的リーク電流の影響 (2012)
  • Author(s): 山本修一郎
  • Organizer: 第73回応用物理学会学術講演会
  • Place of Presentation: 愛媛大学、愛媛県
  • Year and Date: 2012-09-13
• [Presentation] Power-gating ability and power aware design of nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs (2011)
  • Author(s): S.Yamamoto, Y.Shuto, S.Sugahara
  • Organizer: International Magnetics Conference
  • Place of Presentation: Taipei International Convention Center, Taipei, Taiwan
  • Year and Date: 2011-04-28
• [Presentation] Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs
  • Author(s): Shuu'ichirou Yamamoto
  • Organizer: Materials Research Society Spring Meeting
  • Place of Presentation: Moscone Center (USA)
• [Presentation] Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications
  • Author(s): Shuu'ichirou Yamamoto
  • Organizer: IEEE International Semiconductor Conference Dresden-Grenoble (ISCDG)
  • Place of Presentation: MINATEC Campus (France)
• [Presentation] 擬似スピンMOSFETを用いた不揮発性DFF：BETにおける静的リーク電流の影響
  • Author(s): 山本修一郎
  • Organizer: 第73回応用物理学会学術講演会
  • Place of Presentation: 愛媛大学（愛媛県）
• [Presentation] 擬似スピンMOSFET技術を用いたFPGAの不揮発性パワーゲーティング
  • Author(s): 山本修一郎
  • Organizer: 第73回応用物理学会学術講演会
  • Place of Presentation: 愛媛大学（愛媛県）
• [Presentation] 擬似スピンMOSFETを用いた不揮発性デュアルポートSRAMセルの提案とNVPG応用
  • Author(s): 山本修一郎
  • Organizer: 第60回応用物理学関係連合講演会
  • Place of Presentation: 神奈川工科大学（神奈川県）