Device Structure Optimization of MOS Transistors for Reduction of Low Frequency Noise
| Project/Area Number |
22860004
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| Research Category |
Grant-in-Aid for Research Activity Start-up
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| Allocation Type | Single-year Grants |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
KURODA Rihito 東北大学, 大学院・工学研究科, 助教 (40581294)
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| Project Period (FY) |
2010 – 2011
|
| Project Status |
Completed (Fiscal Year 2011)
|
| Budget Amount *help |
¥3,146,000 (Direct Cost: ¥2,420,000、Indirect Cost: ¥726,000)
Fiscal Year 2011: ¥1,508,000 (Direct Cost: ¥1,160,000、Indirect Cost: ¥348,000)
Fiscal Year 2010: ¥1,638,000 (Direct Cost: ¥1,260,000、Indirect Cost: ¥378,000)
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| Keywords | MOSトランジスタ / 1/fノイズ / Random Telegraph Noise / CMOSイメージセンサ / シリコン / ノイズ / Random Telegraph Signalノイズ / MOSFET |
|---|
| Research Abstract |
The noise characteristics of MOS transistors with various device parameters were evaluated using the measurement method that can statistically analyze noise of more than one million transistors. It was confirmed that the appearance probability of random telegraph noise in buried channel structure with buried layer width of 60nm is reduced to 1/60 compared to the standard surface channel structure. The noise reduction mechanism by an introduction of the buried channel structure was clarified. The device structure optimization methodology for low noise MOS transistor was proposed for the realization of very high sensitivity CMOS image sensors.
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Report
(3 results)
Research Products
(71 results)
