Development of 3D CMOS MEMS System Using Inductive-Coupling Inter-Chip Link

• Project/Area Number: 22860011
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Single-year Grants
• Research Field: Electron device/Electronic equipment
• Research Institution: Gunma University
• Principal Investigator: NIITSU Kiichi 群馬大学, 大学院・工学研究科, 助教 (40584785)
• Project Period (FY): 2010 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥3,146,000 (Direct Cost: ¥2,420,000、Indirect Cost: ¥726,000); Fiscal Year 2011: ¥1,508,000 (Direct Cost: ¥1,160,000、Indirect Cost: ¥348,000); Fiscal Year 2010: ¥1,638,000 (Direct Cost: ¥1,260,000、Indirect Cost: ¥378,000)
• Keywords: 集積回路設計 / 半導体集積回路 / CMOS / MEMS / 三次元LSIシステム / 通信回路技術 / 高周波回路技術

Research Abstract

Design of circuit architecture and implementation for wirelessly-connected 3D CMOS MEMS integration was performed. The proposed circuit using pulse-based inductive-coupling link can operate even there is large voltage gap between low-voltage CMOS and high-voltage MEMS.

Research Products

• [Journal Article] Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator (2012)
  • Author(s): Kazuyuki Wakabayashi, Keisuke Kato, Takafumi Yamada, Osamu Kobayashi, Haruo Kobayashi, Fumitaka Abe, Kiichi Niitsu
  • Journal Title: Journal of Electronic Testing : Theoryand Applications Volume: vol.28,no.2 Pages: 152-163
  • Peer Reviewed
• [Journal Article] Architecture of High-Efficiency Digitally-Controlled Class-E Power Amplifier (2011)
  • Author(s): Jiani Ye, Zachary Nosker, KazuyukiWakabayashi, Takuya Yagi, OsamuYamamoto, Nobukazu Takai, Kiichi Niitsu, Keisuke Kato, Takao Ootsuki, Isao Akiyama, and Haruo Kobayashi
  • Journal Title: Key Engineering Materials Volume: vol.487 Pages: 285-295
  • NAID: 10027975592
  • Peer Reviewed
• [Journal Article] A 14 GHz AC-Coupled Clock Distribution Scheme with Phase Averaging Technique Using Sigle LC-VCO and Distributed Phase Interpolators (2011)
  • Author(s): Kiichi Niitsu, Shinmo Kang, Vishal V. Kulkarni, Hiroki Ishikuro, Tadahiro Kuroda
  • Journal Title: IEEE Transactions onVery Large Scale Integration (VLSI) Systems Volume: vol.19,no.11 Pages: 2058-2066
  • Peer Reviewed
• [Journal Article] Analysis and Techniques for Mitigating Interference from Power/Signal Linesand to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power3D System Integration (2011)
  • Author(s): Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, and Tadahiro Kuroda
  • Journal Title: IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems Volume: vol.19,no.10 Pages: 1902-1907
  • Peer Reviewed
• [Journal Article] Architecture of High-Efficiency Digitally-Controlled Class-E Power Amplifier (2011)
  • Author(s): J.Ye, K.Niitsu, H.Kobayashi, et al.
  • Journal Title: Key Engineering Materials Volume: VOL.487 Pages: 285-295
  • DOI: 10.4028/www.scientific.net/kem.497.273
  • NAID: 10027975592
  • Peer Reviewed
• [Journal Article] Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator
  • Author(s): K.Wakabayashi, H.Kobayashi, K.Niitsu, et al.
  • Journal Title: Journal of Electronic Testing : Theory and Applications Volume: (印刷中)
  • Peer Reviewed
• [Journal Article] Analysis and Techniques for Mitigating Interference from Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3D System Integration
  • Author(s): K.Niitsu, Y.Sugimori, Y.Kohama, et al.
  • Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Peer Reviewed
• [Journal Article] A 14GHz AC-Coupled Clock Distribution Scheme with Phase Averaging Technique Using Sigle LC-VCO and Distributed Phase Interpolators
  • Author(s): K.Niitsu, S.Ktang, V.V.Kulkarni, et al.
  • Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Peer Reviewed
• [Presentation] A Clock Jitter Reduction Circuit Using Gated Phase Blending Between Self-Delayed Clock Edges (2012)
  • Author(s): K.Niitsu, T.J.Yamaguchi, H.Kobayashi, et al.
  • Organizer: IEEE Symposium on VLSI Circuits
  • Place of Presentation: ハワイ・アメリカ
  • Year and Date: 2012-06-15
• [Presentation] A Reference-Clock-FreeOn-Chip Timing Jitter Measurement Circuit Using a Cascaded Time Difference Amplifier in 65nm CMOS (2012)
  • Author(s): Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
  • Organizer: IEEE/ACM Asia and South Pacific Design Automations Conference
  • Place of Presentation: シドニー・オーストラリア
  • Year and Date: 2012-02-01
• [Presentation] A Reference-Clock-Free On-Chip Timing Jitter Measurement Circuit Using a Cascaded Time Difference Amplifier in 65nm CMOS (2012)
  • Author(s): K.Niitsu, T.J.Yamaguchi, H.Kobayashi, et al.
  • Organizer: IEEE/ACM Asia and South Pacific Design Automations Conference
  • Place of Presentation: シドニー・オーストラリア
  • Year and Date: 2012-02-01
• [Presentation] Novel AC-DC Direct Converter Design with PFC (2011)
  • Author(s): Yasunori Kobori, Lin Xing, Gao Hong, Naohisa Okamoto, Masaki Ohshima, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
  • Organizer: Paccepted to International Conference on Power Electronics and Power Engineering
  • Place of Presentation: タイ・プーケット
  • Year and Date: 2011-12-21
• [Presentation] Novel AC-DC Direct Converter Design with PFC (2011)
  • Author(s): Y.Kobori, H.Kobayashi, K.Niitsu, et al.
  • Organizer: International Conference on Power Electronics and Power Engineering
  • Place of Presentation: プーケット・タイ
  • Year and Date: 2011-12-21
• [Presentation] Analysis of Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements (2011)
  • Author(s): Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi
  • Organizer: International SoC Design Conference
  • Place of Presentation: 済州・韓国
  • Year and Date: 2011-11-17
• [Presentation] An On-Chip Timing Jitter Measurement Circuit Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier with Duty-Cycle Compensation (2011)
  • Author(s): Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
  • Organizer: IEEE AsianSolid-State Circuits Conference
  • Place of Presentation: 済州・韓国
  • Year and Date: 2011-11-14
• [Presentation] An On-Chip Timing Jitter Measurement Circuit Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier with Duty-Cycle Compensation (2011)
  • Author(s): K.Niitsu, T.J.Yamaguchi, H.Kobayashi, et al.
  • Organizer: IEEE Asian Solid-State Circuits Conference
  • Place of Presentation: 済州・韓国
  • Year and Date: 2011-11-14
• [Presentation] A 0.45V-to-2.7VInductive-Coupling Level Shifter (2011)
  • Author(s): Keita Takatsu, Kiichi Niitsu, Tsunaaki Shidei, Noriyuki Miura, Tadahiro Kuroda
  • Organizer: IEEE Asian Solid-State Circuits Conference
  • Place of Presentation: 北京・中国
  • Year and Date: 2011-11-10
• [Presentation] A Small, Low Power Boost RegulatorOptimized for Energy Harvesting Applications (2011)
  • Author(s): Zachary Nosker, Yasunori Kobori,Haruo Kobayashi, Kiichi Niitsu, Nobukazu Takai, Takeshi Oomori, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto, Jun-ichi Matsuda
  • Organizer: IEEJ International Analog VLSI Workshop
  • Place of Presentation: バリ・インドネシア
  • Year and Date: 2011-11-03
• [Presentation] A Small, Low Power Boost Regulator Optimized for Energy Harvesting Applications (2011)
  • Author(s): Z.Nosker, H.Kobayashi, K Niitsu, et al.
  • Organizer: IEEJ International Analog VLSI Workshop
  • Place of Presentation: バリ・インドネシア
  • Year and Date: 2011-11-03
• [Presentation] Architecture of High-Efficiency Digitally-Controlled Class-E Power Amplifier (2011)
  • Author(s): J.Ye, K.Niitsu, H.Kobayashi, et al.
  • Organizer: IEEJ International Analog VLSI Workshop
  • Place of Presentation: バリ・インドネシア
  • Year and Date: 2011-11-03
• [Presentation] Low-Distortion Single-Tone and Two-Tone Sinewave Generation Algorithms Using ΣΔDAC (2011)
  • Author(s): Takafumi Yamada, Osamu Kobayashi, Keisuke Kato, Kazuyuki Wakabayashi,Haruo Kobayashi, Tatsuji Matsuura, Yuji Yano, Tatsuhiro Gake, Kiichi Niitsu, Nobukazu Takai, Takahiro J. Yamaguchi
  • Organizer: Paccepted to IEEE International Test Conference
  • Place of Presentation: フロリダ・アメリカ
  • Year and Date: 2011-09-21
• [Presentation] Low-Distortion Single-Tone and Two-Tone Sinewave Generation Algorithms Using ΣΔ DAC (2011)
  • Author(s): T.Yamada, H.Kobayashi, K.Niitsu, et al.
  • Organizer: IEEE International Test Conference
  • Place of Presentation: フロリダ・アメリカ
  • Year and Date: 2011-09-21
• [Presentation] A Twistedly-Cascaded Time Difference Amplifier for High Robustness Against Process Variation (2011)
  • Author(s): Naohiro Harigai, Kiichi Niitsu, DaikiOki, Masato Sakurai, Takahiro J.Yamaguchi, Haruo Kobayashi
  • Organizer: International Conference on Solid State Devices and Materials
  • Place of Presentation: 名古屋
  • Year and Date: 2011-09-14
• [Presentation] Low-Distortion Single-Tone and Two-Tone Sinewave Generation Algorithms Using an Arbitrary Waveform Generator (2011)
  • Author(s): Kazuyuki Wakabayashi, Takafumi Yamada,Satoshi Uemori, Osamu Kobayashi,Keisuke Kato, Haruo Kobayashi, KiichiNiitsu, Hiroyuki Miyashita, ShinyaKishigami, Kunihito Rikino, Yuji Yano, Tatsuhiro Gake
  • Organizer: IEEE International Mixed-Signals, Sensors, and Systems Test Workshop
  • Place of Presentation: サンタバーバラ・アメリカ
  • Year and Date: 2011-05-16
• [Presentation] Low-Distortion Single-Tone and Two-Tone Sinewave Generation Algorithms Using an Arbitrary Waveform Generator (2011)
  • Author(s): K.Wakabayashi, H.Kobayashi, K.Niitsu, et al.
  • Organizer: IEEE International Mixed-Signals, Sensors, and Systems Test
  • Place of Presentation: ナニタバーバラ・DSA採択決定
  • Year and Date: 2011-05-16
• [Presentation] Stochastic TDC Architecture withSelf-Calibration (2010)
  • Author(s): Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Nobukazu Takai, Takahiro J.Yamaguchi, Kiichi Niitsu
  • Organizer: IEEE Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: クアラルンプール・マレーシア
  • Year and Date: 2010-12-09
• [Presentation] Stochastic TDC Architecture with Self-Calibration (2010)
  • Author(s): S.Ito, H.Kobayashi, K.Niitsu, et al.
  • Organizer: IEEE Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: クアラルンプール・マレーシア
  • Year and Date: 2010-12-09
• [Presentation] ADC Linearity Test Signal Generation Algorithm (2010)
  • Author(s): Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, KiichiNiitsu, Nobuyoshi Ishikawa
  • Organizer: IEEE Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: クアラルンプール・マレーシア
  • Year and Date: 2010-12-07
• [Presentation] SAR ADC That is Configurable to Optimize Yield (2010)
  • Author(s): Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, TatsujiMatsuura, Nobuyoshi Ishikawa
  • Organizer: IEEE Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: クアラルンプール・マレーシア
  • Year and Date: 2010-12-07
• [Presentation] A 0.45V-to-2.7V Inductive-Coupling Level Shifter (2010)
  • Author(s): K.Takatsu, K.Niitsu, T.Shidei, et al.
  • Organizer: IEEE Asian Solid-State Circuits Conference
  • Place of Presentation: 北京・中国
  • Year and Date: 2010-11-10