| Budget Amount *help |
¥11,050,000 (Direct Cost: ¥8,500,000、Indirect Cost: ¥2,550,000)
Fiscal Year 2013: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2012: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2011: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Outline of Final Research Achievements |
Asynchronous circuits are circuits that do not need any global clock systems. Thus, they have the potential for solving a number of problems, such as clock skew problems, related to global clock systems in the synchronous circuit design. On the other hand, for practice use of asynchronous circuits, various optimization techniques specific to asynchronous circuit design are indispensable. For this purpose, we have developed (1) a tool to determine near-optimal delay values for matched delay elements that are needed for local-handshaking in the bundled-data asynchronous circuits, (2) a tool to generate scripts given to commercial Place & Route CAD tools for packing primitive registers and other instances specified by users, in order to minimize delays that affect the system performance, (3) an idea to implement transition signaling asynchronous circuits very easily using a new type of flip-flops that have multiple-clock inputs and are multiple-edge sensitive.
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