Studies on hierarchies of complexity classes and its application to new evaluation methods for circuit design systems
| Project/Area Number |
23500018
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Fundamental theory of informatics
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| Research Institution | Hiroshima University |
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Principal Investigator |
IWAMOTO Chuzo 広島大学, 工学研究院, 教授 (60274495)
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| Project Period (FY) |
2011-04-28 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
Fiscal Year 2015: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2014: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | 計算の複雑さ |
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| Outline of Final Research Achievements |
It is strongly believed that in order to solve more difficult problems, we need more computational resources, such as space and time. Studies on hierarchies of complexity classes provide a theoretical evidence for such properties. In this research, we investigated the relationship between the depth and the number of nondeterministic gates of circuits. It was shown that every nondeterministic circuit family of depth polylog and size polynomial can be simulated by a nondeterministic circuit family of depth O(log n) and size polynomial by increasing nondeterministic gates polynomially. We also proved the NP-completeness and PSPACE-completeness of several combinatorial problems.
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Report
(7 results)
Research Products
(19 results)
