| Budget Amount *help |
¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Research Abstract |
A test method is developed to detect faults occurred at the wires in VLSI chips, which are not considered in the previous work. Targeting at the defects at wires, contacts, and vias, the weighted fault coverage (WFC) is proposed. Based on the criteria a new technique is presented to compress test pattern lengths while maintaining the defect level.
Triple module redundancy (TMR) has been used to improve system reliability, and the technique is applied to a pipelined processor to enhance the yield and defect level.
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