Dynamically Reconfiguration CABAC Codec Architecture Adaptive to Code Status

Research Project

Project/Area Number	23500064
Research Category	Grant-in-Aid for Scientific Research (C)
Allocation Type	Multi-year Fund
Section	一般
Research Field	Computer system/Network
Research Institution	Okayama Prefectural University
Principal Investigator	KOMOKU Kiyotaka 岡山県立大学, 情報工学部, 助教 (90275371)
Project Period (FY)	2011-04-28 – 2015-03-31
Project Status	Completed (Fiscal Year 2014)
Budget Amount *help	¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000) Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000) Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000) Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Keywords	CABAC / コーデック / H.264 / H.264/AVC / 復号器 / 復号回路 / decoder / 投機処理 / FPGA / 動的再構成
Outline of Final Research Achievements	For CABAC decoding process for block residual data in H.264, the high performance decoding architecture is considered, which predicts the residual data value and speculatively calculate interval subdivision of arithmetic decoding. In first, the code distribution analysis of encoding residual data is investigated.Based on the results, the CABAC architecture which performs a "multi-symbol decoder" and a "1-symbol decoder" in parallel is proposed. The circuit is now implementing.

Report

(5 results)