Chip level timing analysis of 10 billion transistors schale
| Project/Area Number |
23500071
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
TSUKIYAMA Shuji 中央大学, 理工学部, 教授 (90142314)
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | 高信頼化 / 長寿命化 / 見える化 / 信頼性ホットスポット / 経年劣化 / タイミング解析 / 信頼性見える化 / NBTI / GPGPU / ラッシュカレント / 電源配線 / 消費電力モデル / バックワードオイラー法 / 統計的静的遅延解析 / 高信頼性 |
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| Research Abstract |
With the progress of the miniaturization technology of integrated circuits, VLSI chip becomes able to mount more than 10 billion transistors. However, it faces timing reliability issues. This research aims at the technical establishment which conducts timing analysis in a chip level at high speed to the integrated circuit in consideration of manufacture variation, power supply voltage, heat change, and the aged deterioration of a transistor. It aims at visualizing the generating part and factor of a timing error on various physical conditions considered, and raises reliance and extension-of-life-span design of the complicated next-generation integrated circuit.
Through the research period, (A) timing hotspot visualization system, (B) timing analysis system based on thermal and IR drop, and (C) Statistical timing model and analysis system which considers NBTI degradation and variation.
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Report
(4 results)
Research Products
(61 results)
