Floorplan-base Design Environment Technologies for Large-Scale System LSIs
| Project/Area Number |
23560417
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Waseda University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | 高位レベル合成 / フロアプラン / ネットワークオンチップ / 低消費電力設計 / 最適化 / 高位合成 / Floorplanning / Highlevel Synthesis |
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| Research Abstract |
Aiming at efficient design environments for the large system LSIs, the research on High-level Synthesis and Floorplanning has been done.
First, the research on the methods for minimizing power consumption by optimizing the value of the frequency, the power-supply voltage and the threshold voltage of the operation units has been done and new methods based on graph theoretical approach for the linear programming problem, and flow algorithms were developed. Then, a graph theoretical approach for the port assignment problem which is one of the important problems in high-level synthesis was developed. As for the floorplanning problems, floorplanning algorithms for FPGA and 2D/3D Application Specific Network on Chips were developed.
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Report
(4 results)
Research Products
(31 results)
