Study on Design Methodology for Reducing Both of Spatial and Temoporal Random Threshold Variation Based on Potential Control of SRAM Cell Terminals
| Project/Area Number |
23560424
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Fukuoka Institute of Technology |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2011: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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| Keywords | SRAM / SRAMマージン解析 / 時空間ランダムばらつき / ランダムテレグラフノイズ / ランダムドーパントフラクチュエーション / マージンアシスト回路 / コンボリューション / デコンボリューション / RTN / 畳み込み / 逆畳み込み / RDF / 時空間ばらつき / ＲＴＮ / ランダムばらつき / ＳＲＡＭ / Vddのスケーリング / σVtの自己収束 / σVtを擬似的に検出 / インポータンスサンプリング / VLSI設計手法 |
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| Research Abstract |
The purpose of this study is to provide a new design methodology enabling to detect and reduce the spatial/temporal random variations of the threshold voltage in the field after shipment. This study focuses on :(1) concept design for a feasibility study on detection and reduction of the Vt temporally dynamic shift due to Random Telegraph Noise(RTN) (2) physical modeling for the simulation for a feasibility study, and (3) control of offset potential of the terminals of SRAM cell. It has been demonstrated for the first time that the amount of the SRAM overall margin modulation due to the RTN would become unprecedented level and could no longer ignore in the screening design when the tail length of the distribution of the Vt variation for the RTN would exceed that for the random dopant fluctuation (RDF).
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Report
(4 results)
Research Products
(71 results)
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[Journal Article] A Sub-0.3 V Area-Efficient L-Shaped 7T SRA M With Read Bitline Swing Expansion Schemes B ased on Boosted Read-Bitline, Asymmetric-Vth Re ad-Port, and Offset Cell VDD Biasing Techniques2013
Author(s)
Meng-Fan Chang, Ming-Pin Chen, Lai- Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui -Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, We n-Ching Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
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Journal Title
IEEE Journal of Solid State Circuits
Volume: Vol.48, No.10
Pages: 2558-2569
Related Report
Peer Reviewed
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[Journal Article] A High Layer Scalability TSV-Based 3D-SRAM W ith Semi-Master-Slave Structure and Self-Ti med Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms2013
Author(s)
Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Che n, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi
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Journal Title
IEEE Journal of Solid State Circuits
Volume: Vol.48, No.6
Pages: 1521-1529
Related Report
Peer Reviewed
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[Journal Article] Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in A 40nm Fully Functional Embedded SRAM2012
Author(s)
Yen-Huei Chen, Shao-Yu Chou, Li, Q., Wei-Min Chan, Sun, D., Hung-Jen Liao, Ping Wang, Meng-Fan Chang. Hiroyuki Yamauchi
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Journal Title
IEEE Journal of Solid-State-Circuits
Volume: Vol.47, No.4
Pages: 969-980
Related Report
Peer Reviewed
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[Journal Article] Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in A 40nm Fully Functional Embedded SRAM2012
Author(s)
Yen-Huei Chen, Shao-Yu Chou, Quincy Lee, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi
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Journal Title
IEEE Journal of Solid-State Circuits
Volume: Volume: 47
Pages: 969-980
Related Report
Peer Reviewed
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[Journal Article] A LargeσVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme2011
Author(s)
Jui-Jen Wu, Yen-Huei Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu., Wen-Chin Wu, Hiroyuki Yamauchi
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Journal Title
IEEE Journal of Solid-State-Circuits
Volume: Vol.46, No.4
Pages: 815-827
Related Report
Peer Reviewed
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[Presentation] A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques2012
Author(s)
Lai-Fu Chen, Meng-Fan Chang, Ming-Pin Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Ching Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
Organizer
2012 IEEE Symposium on VLSI Circuits
Place of Presentation
ハワイ, 米国
Related Report
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[Presentation] A Larger Stacked Layer Number Scalable TSV-Based 3D-SRAM for High-Performance Universal–Memory -Capacity 3D-IC Platforms2011
Author(s)
M.-F. Chang, W.-C. Wu, C.-S. Lin, P.-F. Chiu, M.-B. Chen, Y.-H. Chen, H.-C. Lai, Z.-H. Lin, S.-S. Sheu, T.-K. Ku, Hiroyuki Yamauchi
Organizer
IEEE Symposium on VLSI Circuits
Place of Presentation
リーガロイアル京都
Related Report
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