Study on a framework for auto generation and optimization of HPC accelerator architectures
| Project/Area Number |
23650021
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku University |
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Principal Investigator |
SANO Kentaro 東北大学, 大学院・情報科学研究科, 准教授 (00323048)
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| Co-Investigator(Renkei-kenkyūsha) |
TAKIZAWA Hiroyuki 東北大学, 大学院・情報科学研究科, 准教授 (70323996)
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2012: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | アクセラレータ / HPC / リコンフィギャラブル計算 / 高位合成 / FPGA / ステンシル計算 / ストリーム計算 / アーキテクチャ記述言語 / 高性能計算 / リコンフィギャラブル |
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| Research Abstract |
We have focused on an algorithm domain of the stencil computation and cellular automata computation that is one of the representative high-performance computations, and then studied a framework to automatically generate their acceleration hardware for reconfigurable computation with FPGAs. In this project, we have developed a stencil compiler for an FPGA-based systolic array and a high-level synthesis compiler for FPGA-based stream-computing accelerators. They are significant and fundamental technologies for highly productive reconfigurable high-performance computation with FPGAs.
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Report
(4 results)
Research Products
(96 results)
