A real-time image recognition system usinga holographic memory and a microelectromechanical system (MEMS)
| Project/Area Number |
23650087
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Perception information processing/Intelligent robotics
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| Research Institution | Shizuoka University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Keywords | 光再構成ゲートアレイ / プログラマブルデバイス / MEMS / DLP / ホログラムメモリ / FPGA / イメージセンサ / レーザ / 画像処理 / 光情報処理 |
|---|
| Research Abstract |
Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such system requires many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Realizing such high-speed real-time image recognition operation is difficult because of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigurable vision architecture using a Micro Electro Mechanical Systems (MEMS), a laser array, a holographic memory, and a VLSI has been developed and its performance has been demonstrated.
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Report
(3 results)
Research Products
(70 results)
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[Presentation] A 7-depth search FPGA Connect6 Solver2013
Author(s)
R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe
Organizer
International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
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[Presentation] FPGA Connect6 Solver with Hardware Sort Units2012
Author(s)
R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, T. Watanabe, Y. Aoyama, M. Seo, M. Watanabe
Organizer
International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
Place of Presentation
Okinawa, Japan
Year and Date
2012-06-01
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[Presentation] An FPGA Connect6 Solver with a Two-Stage Pipelined Evaluation2011
Author(s)
T. Watanabe, R. Moriwaki, Y. Yamaji, Y. Kamikubo, Y. Torigai, Y. Nihira, T. Yoza, Y. Ueno, Y. Aoyama, M. Watanabe
Organizer
IEEE International Conference on Field-Programmable Technology
Place of Presentation
New Delhi, India
Year and Date
2011-12-14
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