| Project/Area Number |
23656230
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Keywords | 電流モード多値集積回路 / 差動対回路 / 電流源制御 / リコンフィギャラブル VLSI / パケット転送制御 / コンフィグレーションメモリ / X ネット / リコンフィギャラブルVLSI / Ｘネット / 多値集積回路 / 電流モード集積回路 / パワーゲーティング |
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| Research Abstract |
A fine-grain multiple-valued reconfigurable VLSI architecture using multiple-valued differential-pair circuits is developed to achieve very high-performance and low- power operations. Multiple-valued signaling is utilized to implement a compact switch block, where multiple-valued signals such as “0", “1", "2" and “3" are transmitted in one line. Also, an autonomous power gating scheme is introduced using two techniques. One is a current-source control based on valid data signal detection. The other is a current-source control such that current sources are turned off within a clock cycle after a logic operation completion signal is detected. Moreover, a register-transfer-level packet routing scheme is introduced to reduce a configuration memory size of a dynamically reconfigurable processor. The register-transfer-driven concept makes the configuration memory size very small, because packets are not required to be provided at all the clock cycles.
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