• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

SoC Defect Level Reduction Based on Critical Area Sampling

Research Project

Project/Area Number 23700062
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system/Network
Research InstitutionNihon University (2013)
Tokyo Metropolitan University (2011-2012)

Principal Investigator

ARAI Masayuki  日本大学, 生産工学部, 助教 (10336521)

Project Period (FY) 2011 – 2013
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Keywords欠陥レベル / 重みつき故障カバレージ / VLSIテスト / クリティカルエリア / クリティカルエリアサンプリング / 欠陥レベル見積 / 重み付き故障カバレージ / SoC欠陥レベル削減 / SoC高信頼設計 / ディペンダブルプロセッサ
Research Abstract

In the field of semiconductor device manufacturing, there is growing problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this we discuss on a accurrate defect levelestimation considering probability of faults, on the basis of logical and layout structures of target circuits. We proposed and evaluated three schemes: weighted fault coverage calculation considering multiple different defect sizes, test pattern reordering algorithm, and critical area estimation without layout data. Experimental results indicated that our proposed schemes can accurately estimate the real defect level, and also that the numbers of test patterns can be reduced.

Report

(4 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Research-status Report
  • 2011 Research-status Report
  • Research Products

    (23 results)

All 2014 2013 2012 2011 Other

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (20 results)

  • [Journal Article] A Highly Reliable Digital Current Control using an Adaptive Sampling Method2014

    • Author(s)
      A. Saysanasongkham, M. Arai, Satoshi Fukumoto, S. Takeuchi, and K. Wada
    • Journal Title

      IEEJ Journal of Industry Applications

      Volume: Vol.3, No.4 (掲載決定)

    • NAID

      130004597586

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Checkpoint Time Arrangement Rotation in Hybrid State Saving with Limited Number of Periodical Checkpoints2013

    • Author(s)
      R. Suzuki, M. Ohara, M. Arai, S. Fukumoto, and K. Iwasaki
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: Vol.E96-D, No.1 Pages: 141-145

    • NAID

      10031167391

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints2013

    • Author(s)
      R. Suzuki, M. Ohara, M. Arai, S. Fukumoto, and K. Iwasaki
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E96.D Issue: 1 Pages: 141-145

    • DOI

      10.1587/transinf.E96.D.141

    • NAID

      10031167391

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Presentation] An Adaptive Approach to Dependable Circuits for a Digital Power Control2013

    • Author(s)
      A. Saysanasongkham, K. Imai, M. Arai, S. Fukumoto, K. Wada
    • Organizer
      International Conference on Dependable Systems and Networks
    • Place of Presentation
      Budapest, Hungary
    • Related Report
      2013 Annual Research Report
  • [Presentation] An Adaptive Sampling Method for a Highly Reliable Digital Control Power Converter2013

    • Author(s)
      K. Wada, A. Saysanasongkham, S. Fukumoto, S. Takeuchi, M. Arai
    • Organizer
      International Future Energy Electronics Conference 2013 (IFEEC 2013)
    • Place of Presentation
      Taichu, Taiwan
    • Related Report
      2013 Annual Research Report
  • [Presentation] Note on Test Pattern Reordering for Weighted Fault Coverage Improvement2013

    • Author(s)
      M. Arai, Y. Nakayama, K. Iwasaki
    • Organizer
      Workshop on RTL and High Level Testing 2013 (WRTLT 2013) 出版者
    • Place of Presentation
      Jiaosi, Taiwan
    • Related Report
      2013 Annual Research Report
  • [Presentation] A Note on Influence of DC-DC Converter Noise in CAN Networks2013

    • Author(s)
      M. Ohara, M. Arai, S. Fukumoto
    • Organizer
      The 19th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2013)
    • Place of Presentation
      Vancouver, Canada
    • Related Report
      2013 Annual Research Report
  • [Presentation] LSIのオープン欠陥クリティカルエリアに関する一検討2013

    • Author(s)
      中山裕太,清水貴弘,新井雅之
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      Tokyo, Japan
    • Related Report
      2012 Research-status Report
  • [Presentation] Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage2012

    • Author(s)
      M. Arai, Y. Shimizu, K. Iwasaki
    • Organizer
      2012 IEEE 21st Asian Test Symposium (ATS 2012)
    • Place of Presentation
      Niigata, Japan(pp. 89-94)
    • Related Report
      2013 Final Research Report
  • [Presentation] Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage2012

    • Author(s)
      M. Arai, Y. Shimizu, K. Iwasaki
    • Organizer
      IEEE Asian Test Symposium
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Research-status Report
  • [Presentation] A Dependable Processor by Using Built in Self Test to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment2012

    • Author(s)
      A. Saysanasongkham, M. Negishi, M. Arai, S. Fukumoto
    • Organizer
      IEEE Pacific Rim International Symposium on Dependable Computig
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Research-status Report
  • [Presentation] Note on Dependable Processor for Periodical Transient Faults under High Electromagnetic Environment2012

    • Author(s)
      A. Saysanasongkham, M. Negishi, M. Arai, S. Fukumoto
    • Organizer
      International Conference on Dependable Systems and Networks (Fast Abstract)
    • Place of Presentation
      Boston, MA, USA
    • Related Report
      2012 Research-status Report
  • [Presentation] レイアウトを考慮した故障カバレージの高精度見積りに関する一考察2012

    • Author(s)
      新井 雅之,清水 貴弘,岩崎 一彦
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      機械振興会館,東京都
    • Related Report
      2011 Research-status Report
  • [Presentation] パイプラインプロセッサ向けカスケードTMRにおける遺伝的アルゴリズムを用いた構成探索2012

    • Author(s)
      新井 雅之,井出 創,岩崎 一彦
    • Organizer
      組込み技術とネットワークに関するワークショップ
    • Place of Presentation
      ホテル松島大観荘,宮城県
    • Related Report
      2011 Research-status Report
  • [Presentation] Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors2011

    • Author(s)
      M. Arai, K. Iwasaki
    • Organizer
      IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2011)
    • Place of Presentation
      Pasadena, CA, USA(pp. 264-271)
    • Related Report
      2013 Final Research Report
  • [Presentation] Self-Calibration Using Functional BIST for Transient-Fault-Tolerant Sequential Circuits in Severe Electromagnetic Environment2011

    • Author(s)
      M. Arai, A. Saysanasongkham, K. Imai,Y. Koyama, S. Fukumoto
    • Organizer
      IEEE 12th International Workshop on RTL and High-Level Testing
    • Place of Presentation
      Jaipur, India(pp. 90-93)
    • Related Report
      2013 Final Research Report
  • [Presentation] パイプラインプロセッサ向けカスケードTMRの欠陥レベル評価に関する一考察2011

    • Author(s)
      新井 雅之,岩崎 一彦
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      首都大学東京秋葉原サテライトキャンパス,東京都
    • Related Report
      2011 Research-status Report
  • [Presentation] 過渡故障を対象とした高信頼化プロセッサの研究動向2011

    • Author(s)
      小山 善文,今井 健太,サイサナソンカム アロムハック,新井 雅之,福本 聡
    • Organizer
      2011年並列/分散/協調処理に関する『鹿児島』サマー・ワークショップ
    • Place of Presentation
      かごしま県民交流センター,鹿児島県
    • Related Report
      2011 Research-status Report
  • [Presentation] Area Per Yield and Defect Level of Cascaded TMR for Pipelined Processors2011

    • Author(s)
      Masayuki Arai and Kazuhiko Iwasaki
    • Organizer
      International Test Conference
    • Place of Presentation
      Disneyland Hotel, Anaheim, CA, USA
    • Related Report
      2011 Research-status Report
  • [Presentation] Self-Calibration Using Functional BIST for Transient-Fault-Tolerant Sequential Circuits in Severe Electromagnetic Environment2011

    • Author(s)
      Masayuki Arai, Aromhack Saysanasongkham, Kenta Imai, Yoshifumi Koyama, and Satoshi Fukumoto
    • Organizer
      IEEE 12th International Workshop on RTL and High Level Testing
    • Place of Presentation
      MNIT, Jaipur, India
    • Related Report
      2011 Research-status Report
  • [Presentation] Area Per Yield and Defect Level of Cascaded TMR for Pipelined Processors2011

    • Author(s)
      Masayuki Arai and Kazuhiko Iwasaki
    • Organizer
      17th IEEE Pacific Rim International Symposium on Dependable Computing
    • Place of Presentation
      Westin Pasadena, CA, USA
    • Related Report
      2011 Research-status Report
  • [Presentation] レイアウトを考慮したブリッジ/オープン故障カバレージの高精度見積法

    • Author(s)
      新井雅之, 清水貴弘, 岩崎一彦
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      Tokyo, Japan
    • Related Report
      2012 Research-status Report
  • [Presentation] クリティカルエリア解析に基づく故障カバレージ見積りに関する一考察

    • Author(s)
      清水貴弘, 中山裕太, 新井雅之, 岩崎一彦
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      Gifu, Japan
    • Related Report
      2012 Research-status Report

URL: 

Published: 2011-08-05   Modified: 2019-07-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi