SoC Defect Level Reduction Based on Critical Area Sampling
| Project/Area Number |
23700062
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Nihon University (2013)
Tokyo Metropolitan University (2011-2012) |
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Principal Investigator |
ARAI Masayuki 日本大学, 生産工学部, 助教 (10336521)
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
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| Keywords | 欠陥レベル / 重みつき故障カバレージ / VLSIテスト / クリティカルエリア / クリティカルエリアサンプリング / 欠陥レベル見積 / 重み付き故障カバレージ / SoC欠陥レベル削減 / SoC高信頼設計 / ディペンダブルプロセッサ |
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| Research Abstract |
In the field of semiconductor device manufacturing, there is growing problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this we discuss on a accurrate defect levelestimation considering probability of faults, on the basis of logical and layout structures of target circuits. We proposed and evaluated three schemes: weighted fault coverage calculation considering multiple different defect sizes, test pattern reordering algorithm, and critical area estimation without layout data. Experimental results indicated that our proposed schemes can accurately estimate the real defect level, and also that the numbers of test patterns can be reduced.
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Report
(4 results)
Research Products
(23 results)
