Research on delay test techniques for ultra-low power designs
| Project/Area Number |
23700065
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Waseda University |
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Principal Investigator |
SHI YOUHUA 早稲田大学, 高等研究所, 准教授 (70409655)
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2013: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Keywords | 低消費電力設計 / LSI設計 / 高信頼設計 / 低消費電力化 / 遅延解析 / VLSI設計技術とCAD / ディペンダブルコンピューティング / VLSI 設計技術とCAD |
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| Research Abstract |
Recently, low power VLSI designs have gained a lot of research attentions from both industry and academia. Consequently, reliability becomes an important design issue in state-of-the-art low power designs. Facing this design challenge, we conducted the following researches on 1) reliable sub-threshold circuit design, 2) wire delay aware low power synthesis methods, and 3) timing error detection method to guarantee the reliability of low power VLSI designs.
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Report
(4 results)
Research Products
(23 results)
