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Dedicated design platform for via-programmable device using physical synthesis

Research Project

Project/Area Number 23700066
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system/Network
Research InstitutionMeijo University

Principal Investigator

YOSHIKAWA Masaya  名城大学, 理工学部, 教授 (50373098)

Project Period (FY) 2011 – 2012
Project Status Completed (Fiscal Year 2012)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
Keywordsビアプログラマブルデバイス / ストラクチャード ASIC / ストラクチャードASIC
Research Abstract

In this study, we developed the dedicated design platform for via-programmable device using physical synthesis. Specifically, this study consists of the following four themes: (1) Physical synthesis aware logic optimization, (2) Timing estimation for the dedicated via-programmable device, (3) Layout algorithm for physical synthesis, and (4) Timing driven detailed routing for the dedicated via-programmable device. Several fundamental techniques for the dedicated design platform have been developed in this study.

Report

(3 results)
  • 2012 Annual Research Report   Final Research Report ( PDF )
  • 2011 Research-status Report
  • Research Products

    (7 results)

All 2012

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (5 results)

  • [Journal Article] Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System2012

    • Author(s)
      R.Hori, T.Kitamori, T.Ueoka, M.Yoshikawa, T.Fujino
    • Journal Title

      IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: Vol.E95-A, No.12 Pages: 2182-2190

    • NAID

      10031161351

    • Related Report
      2012 Annual Research Report 2012 Final Research Report
    • Peer Reviewed
  • [Journal Article] mproved Via-Programmable Structured ASIC VPEX3 and its Evaluation2012

    • Author(s)
      R.Hori, T.Kitamori, T.Ueoka, M.Yoshikawa, T.Fujino
    • Journal Title

      IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: Vol.E95-A, No.9 Pages: 1518-1528

    • Related Report
      2012 Annual Research Report
    • Peer Reviewed
  • [Presentation] The Development of CAD System for Via Programmable Structured ASIC VPEX32012

    • Author(s)
      R.Hori, M.Yoshikawa, T.Fujino
    • Organizer
      Proc. of The 17th Workshop on Synthesis And System Integration of Mixed Information technologies. pp.470-475
    • Related Report
      2012 Final Research Report
  • [Presentation] ビアプログラマブルASICアーキテクチャVPEXの消費電力評価と面積・遅延性能評価2012

    • Author(s)
      大谷拓,堀遼平,北森達也,上岡泰輔,吉川雅弥,藤野毅
    • Organizer
      電子情報通信学会,信学技報
    • Related Report
      2012 Final Research Report
  • [Presentation] ビアプログラマブルロジックVPEXの配置配線ツールを用いた性能評価2012

    • Author(s)
      大谷拓,堀遼平,上岡泰輔,吉川雅弥,藤野毅
    • Organizer
      電子情報通信学会
    • Place of Presentation
      九州大学医学部百年講堂
    • Related Report
      2012 Annual Research Report
  • [Presentation] The Development of CAD System for Via Programmable Structured ASIC VPEX32012

    • Author(s)
      R.Hori, M.Yoshikawa, T.Fujino
    • Organizer
      The 17th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      ビーコンプラザ(別府)
    • Related Report
      2011 Research-status Report
  • [Presentation] ビアプログラマブルASICアーキテクチャVPEXの消費電力評価と面積・遅延性能評価2012

    • Author(s)
      大谷拓,堀遼平,北森達也,上岡泰輔,吉川雅弥,藤野毅
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      ビーコンプラザ(別府)
    • Related Report
      2011 Research-status Report

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Published: 2011-08-05   Modified: 2019-07-29  

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