Development of the Reconfigurable Host-Based IPS Processor with the Multiplexed Data Bus
| Project/Area Number |
23700068
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Hirosaki University |
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Principal Investigator |
SATO Tomoaki 弘前大学, 総合情報処理センター, 准教授 (00336992)
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2011: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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| Keywords | ネットワークセキュリティ技術 / 不正侵入防御システム / 不正アクセス防御システム / 多重化バス / 組み込みＣＰＵ / シフトレジスタ / IPS / ウェーブパイプライン / CPU / ファイアウォール / WEP / 低消費電力 |
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| Research Abstract |
The Reconfigurable Host-Based IPS Processor is developed for a highly accurate detection of unauthorized computer access in a smartphone or a personal computer with battery operation. The processor is composed of MAC Unit, Firewall Logic Unit with LUTs for Intrusion Prevention and a CPU. Each unit is connected with a bus to carry Ethernet frames. That is, a huge number of wiring is required. In this study, a multiplexed bus is developed by using wave-pipeline technique aiming at a highly effective packet forwarding. The bus is evaluated, and the multiplexing operation of the bus is confirmed. In addition, the performance of the CPU needed in the processor is evaluated and cipher strength of the wireless LAN in the processor is strengthened.
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Report
(4 results)
Research Products
(19 results)
