| Budget Amount *help |
¥18,070,000 (Direct Cost: ¥13,900,000、Indirect Cost: ¥4,170,000)
Fiscal Year 2014: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2013: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2012: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000)
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| Outline of Final Research Achievements |
We have developed a processor architecture which features restricted dynamic reconfiguration of datapath for the sake of keeping general-purposeness and low-powerness at the same time, targeting toward embedded system application where those two features are mandatory requirement. We have named the architecure is named Control-Flow Driven Data-Flow Switching (CDDS), and conducted detailed design and test chip design. Through measurement of the fabricated test chip, we have confirmed reasonable power reduction by the proposed architecture. We have presented the results at one of major international conferences in circuit design, A-SSCC, and showed demonstration of the chip successfully.
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