Accurate measurement and statistical analysis of gate leakage current of MOSFETs with atomically flat interface
Project/Area Number |
24360129
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Research Category |
Grant-in-Aid for Scientific Research (B)
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Allocation Type | Partial Multi-year Fund |
Section | 一般 |
Research Field |
Electron device/Electronic equipment
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Research Institution | Tohoku University |
Principal Investigator |
SUGAWA Shigetoshi 東北大学, 工学(系)研究科(研究院), 教授 (70321974)
|
Co-Investigator(Renkei-kenkyūsha) |
KURODA Rihito 東北大学, 大学院工学研究科, 准教授 (40581294)
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Project Period (FY) |
2012-04-01 – 2015-03-31
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Project Status |
Completed (Fiscal Year 2014)
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Budget Amount *help |
¥18,980,000 (Direct Cost: ¥14,600,000、Indirect Cost: ¥4,380,000)
Fiscal Year 2014: ¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2013: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2012: ¥12,090,000 (Direct Cost: ¥9,300,000、Indirect Cost: ¥2,790,000)
|
Keywords | 電子デバイス・機器 / 電子デバイス・集積回路 / MOSFET / シリコン / リーク電流 / ストレス誘起電流 / 平坦化 |
Outline of Final Research Achievements |
Atomically flattening technology of gate insulator film/Si interface was introduced to a 0.22 um CMOS LSI manufacturing technology. It was clarified that the atomic level flatness is obtained at the interface of miniaturized MOSFET by introducing the Si surface flattening process at a temperature less than 850 C right before gate insulator film formation process step. The array test circuit was fabricated based on the introduced technology. By measuring gate current of over 80000 MOSFETs with gate insulator film thickness of 7.7 nm within 80 sec with 10aA accuracy using the developed high accuracy statistical measurement technology, it was confirmed that the appearance probability of MOSFETs with large gate current is decreased by one order of magnitude in comparison to the conventional MOSFETs of which roughness at the gate insulator film/Si interface is about 1 nm.
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Report
(4 results)
Research Products
(30 results)
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[Journal Article] Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers2015
Author(s)
Tetsuya Goto, Rihito Kuroda, Naoya Akagawa, Tomoyuki Suwa, Akinobu Teramoto, Xiang Li, Toshiki Obara, Daiki Kimoto, Shigetoshi Sugawa, Tadahiro Ohmi, Yutaka Kamata, Yuki Kumagai, and Katsuhiko Shibusawa
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Journal Title
Japanese Journal of Applied Physics
Volume: 54
Issue: 4S
Pages: 04DA04-04DA04
DOI
NAID
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Peer Reviewed
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[Presentation] Atomically Flattening of Si Surface of SOI and Isolation-patterned Wafers2014
Author(s)
T. Goto, R. Kuroda, N. Akagawa, T. Suwa, A. Teramoto, X. Li, S. Sugawa, T. Ohmi, Y. Kumagai, Y. Kamata, and T. Shibusawa
Organizer
2014 International Conference on Solid State Devices and Materials
Place of Presentation
つくば国際会議場(茨城県・つくば市)
Year and Date
2014-09-08 – 2014-09-11
Related Report
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[Presentation] A Novel Analysis of Oxide Breakdown based on Dynamic Observation using Ultra-High Speed Video Capturing Up to 10,000,000 Frames Per Second2014
Author(s)
Rihito Kuroda, Fan Shao, Daiki Kimoto, Kiichi Furukawa, Hidetake Sugo, Tohru Takeda, Ken Miyauchi, Yasuhisa Tochigi, Akinobu Teramoto and Shigetoshi Sugawa
Organizer
2014 IEEE International Reliability Physics Symposium
Place of Presentation
Waikoloa, USA
Year and Date
2014-06-03 – 2014-06-05
Related Report
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[Presentation] Analyzing Correlation between Multiple Traps in RTN Characteristics2014
Author(s)
Toshiki Obara, Akinobu Teramoto, Akihiro Yonezawa, Rihito Kuroda, Shigetoshi Sugawa, and Tadahiro Ohmi
Organizer
Toshiki Obara, Akinobu Teramoto, Akihiro Yonezawa, Rihito Kuroda, Shigetoshi Sugawa, and Tadahiro Ohmi
Place of Presentation
Waikoloa, USA
Year and Date
2014-06-03 – 2014-06-05
Related Report
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