studies on high-reliability timing design methods for logic circuits using advanced devices

• Project/Area Number: 24500061
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyoto University
• Principal Investigator: TAKAGI Kazuyoshi 京都大学, 情報学研究科, 准教授 (70273844)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Project Status: Completed (Fiscal Year 2014)
• Budget Amount: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000); Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2012: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
• Keywords: 論理回路 / 論理関数 / タイミング設計 / レイアウト設計 / 超伝導単一磁束量子デバイス

Outline of Final Research Achievements

We obtained the following two results.
1. We developed an automatic placement and routing method for integrated circuits using superconducting single-flux-quantum logic device which can realize super high-speed and low-power consumption logic circuits.
2. Adiabatic quantum-flux-parametron is a super low-power logic device and attempts to build large scale circuits with the device have begun recently. The basic logic elements are majority gates. We enumerated minimum depth circuits for all five-variable logic functions using three-input majority gates.The result is useful as the basis for logic synthesis method for the device.

Research Products

• [Presentation] 単一磁束量子回路のパルス到着タイミングを最適化する配置配線手法 (2015)
  • Author(s): 西村翔、高木一義、高木直史
  • Organizer: 電子情報通信学会総合大会
  • Place of Presentation: 立命館大学 びわこ・くさつキャンパス、滋賀県草津市
  • Year and Date: 2015-03-11
• [Presentation] 3入力多数決ゲートを用いた5変数論理関数の最小段数回路 (2015)
  • Author(s): 守家大雄、高木一義、高木直史
  • Organizer: 2014年冬のLAシンポジウム
  • Place of Presentation: 京都大学 吉田キャンパス北部構内 数理解析研究所、京都府京都市
  • Year and Date: 2015-01-28
• [Presentation] Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Three-Input Majority Gates (2014)
  • Author(s): M.Moriya, K.Takagi, N.Takagi
  • Organizer: Superconducting SFQ VLSI Workshop (SSV 2014)
  • Place of Presentation: National Institute of Information and Communications Technology (NICT), Kobe, Japan
  • Year and Date: 2014-12-01
• [Presentation] Automatic Placement and Routing of a Pipelined Module in an RSFQ Logic Circuit with Timing Constraints (2014)
  • Author(s): S.Nishimura, K.Takagi, N.Takagi
  • Organizer: Superconducting SFQ VLSI Workshop for Young Scientists (SSV2014-YS)
  • Place of Presentation: Nagoya University
• [Presentation] 単一磁束量子回路向けの論理ゲート配置手法
  • Author(s): 西村翔, 高木一義, 高木直史
  • Organizer: 2013年電子情報通信学会総合大会
  • Place of Presentation: 岐阜大学