Design method of optimized asynchronous pipelines using control-flow graphs
| Project/Area Number |
24500065
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Multi-year Fund |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Okayama University |
|---|
Principal Investigator |
|
|---|
| Project Period (FY) |
2012-04-01 – 2016-03-31
|
| Project Status |
Completed (Fiscal Year 2015)
|
| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2014: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2013: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
Fiscal Year 2012: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
|
|---|
| Keywords | 非同期式回路 / 制御フローグラフ / 依存性グラフ / 簡単化 / パイプライン / SDI遅延モデル / 状態遷移 |
|---|
| Outline of Final Research Achievements |
Pipelines are effective for improving performance of asynchronous circuits, which are expected to reduce power consumption and electromagnetic radiation by eliminating clock signals. Although pipelining using control-flow graphs are effective for reducing circuit size, there remains some redundant circuitry increasing the control circuits. In this research, an algorithm for simplifying pipelined control-flow graphs by eliminating redundant nodes. Also, an improved algorithm reduces computational complexity for the simplification.
|
Report
(5 results)
Research Products
(5 results)
