| Budget Amount *help |
¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
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| Outline of Final Research Achievements |
In this project, we have studied on fault tolerant sequential circuits for a new transient fault model under highly electromagnetic environment, which is characterized by simultaneous multiple occurrences and periodicity. The major results are as follows.
1) We have proposed a scheme to construct highly reliable processors that can tolerate against simultaneous multi-bit transient faults which occur synchronously with the switching noise. The proposed scheme applies Built-in Self Test (BIST) logic, which is implemented beside the target circuit to measure the duration of the transient faults.
2) We have proposed an adaptive sampling method for a digital control current-mode power converter circuit on an FPGA (Field Programmable Gate Array) with the PWM (Pulse Width Modulator) sawtooth carrier waveform. To avoid the switching noises, sampling timing of the AD converter will be tuned adaptively regarding the duty ratio of each switching cycle.
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