Study on fully digital ratio-less SRAM design for avoiding the variability and aging effects of device characteristics
| Project/Area Number |
24560408
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
NAKAMURA KAZUYUKI 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2013: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | CMOS / SRAM / LSI / 素子ばらつき / 経年劣化 / マージン / レシオレス / 低電圧 / メモリ / ノイズマージン / SNM / スタティックノイズマージ / スタティックノイズマージン |
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| Outline of Final Research Achievements |
The Ratio-less SRAM technology which features fully digital operation and large operating margin for device variability and aging effect was studied. Several test chips: Mosaic SRAM cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation, variable Vth-TEGs for emulating the threshold voltage shift, and 1Kbit SRAM test chips for comparing the minimum operating supply voltage between conventional 6T-SRAM and developed ratio-less SRAM were developed. Measured results from these test chips showed the higher immunity for device variability and the superior low supply voltage operation of ratio-less SRAM than conventional SRAMs.
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Report
(4 results)
Research Products
(7 results)
