Study on fully digital ratio-less SRAM design for avoiding the variability and aging effects of device characteristics

• Project/Area Number: 24560408
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: NAKAMURA KAZUYUKI 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Project Status: Completed (Fiscal Year 2014)
• Budget Amount: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000); Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2013: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000); Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
• Keywords: CMOS / SRAM / LSI / 素子ばらつき / 経年劣化 / マージン / レシオレス / 低電圧 / メモリ / ノイズマージン / SNM / スタティックノイズマージ / スタティックノイズマージン

Outline of Final Research Achievements

The Ratio-less SRAM technology which features fully digital operation and large operating margin for device variability and aging effect was studied. Several test chips: Mosaic SRAM cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation, variable Vth-TEGs for emulating the threshold voltage shift, and 1Kbit SRAM test chips for comparing the minimum operating supply voltage between conventional 6T-SRAM and developed ratio-less SRAM were developed. Measured results from these test chips showed the higher immunity for device variability and the superior low supply voltage operation of ratio-less SRAM than conventional SRAMs.

Research Products

• [Journal Article] Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation (2015)
  • Author(s): Takahiro Kondo, Hiromasa Yamamoto, Satoko Hoketsu, Hitoshi Imi, Hitoshi Okamura, Kazuyuki Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: ５４ Issue: 4S Pages: 04DD11-04DD11
  • DOI: 10.7567/jjap.54.04dd11
  • NAID: 120006782185
  • Peer Reviewed / Open Access / Acknowledgement Compliant
• [Presentation] A Measurement of Ratio-less 12-transistor SRAM cell Operation at Ultra-low Supply-voltage (2014)
  • Author(s): T. Kondo, H. Yamamoto, H. Imi, H. Okamura, K. Nakamura
  • Organizer: International Conference on Solid State Devices and Materials(SSDM)
  • Place of Presentation: Tsukuba, Japan
  • Year and Date: 2014-09-10
• [Presentation] ＣＭＯＳ ＳＲＡＭセルのしきい値電圧ばらつき耐性評価用ＴＥＧの設計及び評価 (2014)
  • Author(s): 伊見 仁，徳丸 翔吾，岡村 均，中村 和之
  • Organizer: LSIとシステムのワークショップ2014
  • Place of Presentation: 北九州国際会議場
  • Year and Date: 2014-05-26
• [Presentation] Mosaic SRAM Cell TEGs with Intentionally-added Device Variability for Confirming the Ratio-less SRAM Operation (2013)
  • Author(s): Hitoshi Okamura, Takahiko Saito, Hiroaki Goto, Masahiro Yamamoto and Kazuyuki Nakamura
  • Organizer: IEEE International Conference on Microelectronic Test Structures (ICMTS 2013)
  • Place of Presentation: Osaka, Japan
• [Presentation] A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM Design (2013)
  • Author(s): Saito, T. ; Okamura, H. ; Yamamoto, H. ; Nakamura, K.
  • Organizer: 2012 4th IEEE International Memory Workshop (IMW)
  • Place of Presentation: Milan, Italy
• [Presentation] Ratio-less 10Tr-SRAMセルとColumn Retention Loop構造による完全デジタルSRAMの設計及び評価
  • Author(s): 山本裕允、齋藤貴彦、岡村均、中村和之
  • Organizer: LSIとシステムのワークショップ 2013
  • Place of Presentation: 北九州国際会議場
• [Patent(Industrial Property Rights)] 半導体記憶装置 (2013)
  • Inventor(s): 中村和之、齊藤貴彦、岡村均
  • Industrial Property Rights Holder: 中村和之、齊藤貴彦、岡村均
  • Industrial Property Rights Type: 特許
  • Filing Date: 2013-03-22
  • Overseas