A Circuit Level Stabilizing Technique for Implementing Film Computers
| Project/Area Number |
24650020
|
|---|
| Research Category |
Grant-in-Aid for Challenging Exploratory Research
|
| Allocation Type | Multi-year Fund |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Nara Institute of Science and Technology |
|---|
Principal Investigator |
NAKASHIMA YASUHIKO 奈良先端科学技術大学院大学, 情報科学研究科, 教授 (00314170)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
HARA Yuko 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20640999)
|
|---|
| Co-Investigator(Renkei-kenkyūsha) |
URAOKA Yukiharu 奈良先端科学技術大学院大学, 物質創成科学研究科, 教授 (20314536)
|
|---|
| Project Period (FY) |
2012-04-01 – 2015-03-31
|
| Project Status |
Completed (Fiscal Year 2014)
|
| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2013: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
|
|---|
| Keywords | ディペンダブル / 小型CPU / エミュレーション / 高信頼化CAD / 耐故障アクセラレータ / PPC / IGZO / 超小型CPU / 回路冗長化 / 多数演算器アクセラレータ / 新素材 / フレキシブルコンピュータ / 高信頼化 / 酸化亜鉛 |
|---|
| Outline of Final Research Achievements |
uClinux for 32bit computer has successfully worked on tiny 8bit CPU on FPGA. A physical layout of the tiny CPU with only 10000 transistors has been completed. An instruction level workaround technique for bypassing hardware defects, PPC (Partially Programmable Circuit) technique for bypassing logic defects, hardware level defect detector without TMR (Triple Module Redundancy) and reconfiguration technique for defect isolation are established. A dependable FU array accelerator has been designed and the high-dependability has been observed by error injection with an alpha-particle generator.
|
Report
(4 results)
Research Products
(30 results)
-
-
-
-
-
-
-
-
-
-
-
[Presentation] Better-than-DMR techniques for Yield Improvement2014
Author(s)
Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima
Organizer
The 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines
Place of Presentation
Boston, Massachusetts
Year and Date
2014-05-11 – 2014-05-13
Related Report
-
-
-
-
[Presentation] Novel Area-Efficient Technique for Yield Improvement2014
Author(s)
Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima
Organizer
Workshop on Design Automation for Understanding Hardware Designs, Design Automation and Test in Europe (DATE)
Place of Presentation
Maritim Hotel & Internationales Congress Center (Dresden)
Related Report
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
