| Project/Area Number |
24650022
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
WEN Xiaoqing 九州工業大学, 大学院情報工学研究院, 教授 (20250897)
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| Co-Investigator(Kenkyū-buntansha) |
MIYASE Kohei 九州工業大学, 情報工学研究院, 助教 (30452824)
KAJIHARA Seiji 九州工業大学, 情報工学研究院, 教授 (80252592)
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2014: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | LSIテスト / スキャンテスト電力 / クロックスキュー / 最適電力テスト / 低電力テスト / テスト品質 / IR-Drop / テストデータ / テスト電力調整 / 遅延テスト / 微小遅延故障 / 活性化パス / 高信頼化 / 高品質化 |
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| Outline of Final Research Achievements |
With the ever-increasing circuit scales, ever-decreasing power supply voltages, and ever-increasing clock speeds, test quality degradation (over-test as well as under-test), which cannot be sufficiently addressed by previous solutions, has become a major problem that prevents the creation of high-quality and low-cost LSIs. In this research, we first pointed out that unbalanced switching activity around test clock paths causes severe clock skew, which is one of the major causes for test quality degradation. Based on this observation, we proposed and evaluated unique solutions for conducing vector-based test clock skew assessment as well as solutions for test generation and design-for-test for mitigating test clock skews.
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