| Budget Amount *help |
¥26,650,000 (Direct Cost: ¥20,500,000、Indirect Cost: ¥6,150,000)
Fiscal Year 2015: ¥8,190,000 (Direct Cost: ¥6,300,000、Indirect Cost: ¥1,890,000)
Fiscal Year 2014: ¥6,890,000 (Direct Cost: ¥5,300,000、Indirect Cost: ¥1,590,000)
Fiscal Year 2013: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2012: ¥7,020,000 (Direct Cost: ¥5,400,000、Indirect Cost: ¥1,620,000)
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| Outline of Final Research Achievements |
In this research project, the researcher has studied and proposed processor architecture with in-order and out-of-order execution systems. In this architecture, most instructions are executed by a simple and power efficient in-order execution system while processing the remaining instructions by a reduced high-performance out-of-order execution system. As a result, power consumption is greatly reduced while maintaining processor performance. In this research project, proposals and evaluation results on this new architecture were published in journals and symposium papers, including IEEE/ACM International Symposium on Microarchitecture (MICRO), which is the top conference in this field.
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