Accelerating computations using many-core architecture for FPGAs
Project/Area Number |
24700033
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Research Category |
Grant-in-Aid for Young Scientists (B)
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Allocation Type | Multi-year Fund |
Research Field |
Software
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Research Institution | Hiroshima University |
Principal Investigator |
Yasuaki Ito 広島大学, 工学(系)研究科(研究院), 准教授 (40397964)
|
Project Period (FY) |
2012-04-01 – 2016-03-31
|
Project Status |
Completed (Fiscal Year 2015)
|
Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2014: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2013: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
|
Keywords | FPGA / DSPブロック / ブロックRAM / ハフ変換 / マルチコアプロセッサ / 多倍長演算 / 組込みDSPブロック / 組込みブロックRAM / 並列処理 / メニーコア / DSP block / Block RAM / サポートベクターマシン |
Outline of Final Research Achievements |
In this research, I tried to make developing environments of many-core architecture for FPGAs. First, we proposed efficient FPGA implementations of line and circle detection that is efficiently performed with DSP blocks and block RAMs on the FPGA by separating the parameter space and arranging many processing cores. The implementations can run faster than existing methods. Using these results, we proposed a tiny general-purpose processor that supports multiple-length computation using one DSP blocks and two block RAMs and implemented it on the FPGA. Using this processor, we showed that users can develop software programs that is almost the same performance as the specific circuits.
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Report
(5 results)
Research Products
(9 results)