Accelerating computations using many-core architecture for FPGAs

• Project/Area Number: 24700033
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Software
• Research Institution: Hiroshima University
• Principal Investigator: Yasuaki Ito 広島大学, 工学(系)研究科(研究院), 准教授 (40397964)
• Project Period (FY): 2012-04-01 – 2016-03-31
• Project Status: Completed (Fiscal Year 2015)
• Budget Amount: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000); Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2014: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2013: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
• Keywords: FPGA / DSPブロック / ブロックRAM / ハフ変換 / マルチコアプロセッサ / 多倍長演算 / 組込みDSPブロック / 組込みブロックRAM / 並列処理 / メニーコア / DSP block / Block RAM / サポートベクターマシン

Outline of Final Research Achievements

In this research, I tried to make developing environments of many-core architecture for FPGAs. First, we proposed efficient FPGA implementations of line and circle detection that is efficiently performed with DSP blocks and block RAMs on the FPGA by separating the parameter space and arranging many processing cores. The implementations can run faster than existing methods. Using these results, we proposed a tiny general-purpose processor that supports multiple-length computation using one DSP blocks and two block RAMs and implemented it on the FPGA. Using this processor, we showed that users can develop software programs that is almost the same performance as the specific circuits.

Research Products

• [Journal Article] An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA (2014)
  • Author(s): Xin Zhou, Yasuaki Ito, and Koji Nakano
  • Journal Title: Proc. of International Symposium on Computing and Networking Volume: 1 Pages: 447-452
  • DOI: 10.1109/candar.2014.32
  • Peer Reviewed
• [Journal Article] An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA (2014)
  • Author(s): Xin Zhou, Yasuaki Ito, Koji Nakano
  • Journal Title: Proc. of International Parallel and Distributed Processing Symposium Workshops Volume: 1 Pages: 762-770
  • DOI: 10.1109/ipdpsw.2014.88
  • NAID: 110009947081
  • Peer Reviewed
• [Journal Article] Implementations of the Hough Transform on the Embedded Multicore Processors (2014)
  • Author(s): Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano
  • Journal Title: International Journal of Networking and Computing Volume: 4 Pages: 174-188
  • NAID: 130005475352
  • Peer Reviewed
• [Journal Article] An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA (2013)
  • Author(s): Xin Zhou, Yasuaki Ito and Koji Nakano
  • Journal Title: Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs Volume: 1 Pages: 85-90
  • DOI: 10.1109/mcsoc.2013.29
  • Peer Reviewed
• [Journal Article] A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA (2013)
  • Author(s): Yuki Ago, Koji Nakano and Yasuaki Ito
  • Journal Title: Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs Volume: 1 Pages: 91-96
  • DOI: 10.1109/mcsoc.2013.30
  • Peer Reviewed
• [Journal Article] A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles (2012)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Journal Title: International Journal of Networking and Computing Volume: Vol. 2, No. 1 Pages: 269-290
  • NAID: 130005475365
  • Peer Reviewed
• [Presentation] A flexible-length-arithmetic processor based on FDFM approach in FPGAs (2015)
  • Author(s): Tatsuya Kawamoto, Yasuaki Ito, Koji Nakano
  • Organizer: International Symposium on Computing and Networking
  • Place of Presentation: 札幌市
  • Year and Date: 2015-12-08
  • Int'l Joint Research
• [Presentation] An FPGA Implementation of Hough Transform using DSP blocks and block RAMs (2012)
  • Author(s): Xin Zhou, Yasuaki Ito and Koji Nakano
  • Organizer: The Second International Workshop on Networking, Computing, Systems, and Software
  • Place of Presentation: 沖縄県那覇市
• [Presentation] An Efficient Implementation of a Support Vector Machine in the FPGA (2012)
  • Author(s): Yuki Ago, Yasuaki Ito and Koji Nakano
  • Organizer: The Second International Workshop on Networking, Computing, Systems, and Software
  • Place of Presentation: 沖縄県那覇市