• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

An Structural Test Method of Analog Circuits for Improving Test Efficiency of System LSIs

Research Project

Project/Area Number 24700043
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system/Network
Research InstitutionThe University of Tokyo

Principal Investigator

KOMATSU Satoshi  東京大学, 大規模集積システム設計教育研究センター, 准教授 (90334325)

Project Period (FY) 2012-04-01 – 2014-03-31
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2013: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
KeywordsVLSI設計技術 / VLSI設計技術
Research Abstract

In this study, we have studied on improving test efficiency of system LSIs. To achieve such efficient manufacturing test, we introduced structural test methods which are usually used in testing of digital circuits into testing of analog circuits.
We have evaluated transfer characteristics between input stimulus and output signals by using SPICE simulator. In addition, we also proposed and evaluated on-chip signal sampler circuits which are necessary for on-chip testing of analog circuits. We designed and evaluated analog-to-digital conversion circuits and time-to-digital conversion circuits. The experimental results showed that those circuits can be applied for efficient testing of analog circuits with high precision.

Report

(3 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Research-status Report
  • Research Products

    (3 results)

All 2014 2013

All Presentation (3 results)

  • [Presentation] A Subsampling Stochastic Coarse-Fine ADC with SNR 55.3dB and >5.8TS/s Effective Sample Rate for an on-Chip Signal Analyzer2014

    • Author(s)
      James Tandon, Takahiro Yamaguchi, Satoshi Komatsu, Kunihiro Asada
    • Organizer
      IEEE International Symposium on Circuits and Systems 2014
    • Place of Presentation
      Melbourne, Australia
    • Year and Date
      2014-06-02
    • Related Report
      2013 Annual Research Report 2013 Final Research Report
  • [Presentation] A Stochastic Sampling Time-to-Digital Converter with Tunable 180-770fs Resolution, INL less than 0.6LSB, and Selectable Dynamic Range Offset2013

    • Author(s)
      James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, and Kunihiro Asada
    • Organizer
      IEEE Custom Integrated Circuits Conference (CICC)
    • Place of Presentation
      San Jose, CA, USA
    • Year and Date
      2013-09-11
    • Related Report
      2013 Annual Research Report 2013 Final Research Report
  • [Presentation] On-chip Measurement / Monitor Circuits Based-on Stochastic Approach2013

    • Author(s)
      S. Komatsu
    • Organizer
      2013 International Test Conference (Elevator Talk)
    • Place of Presentation
      Anaheim, CA, USA
    • Year and Date
      2013-09-10
    • Related Report
      2013 Annual Research Report 2013 Final Research Report

URL: 

Published: 2013-05-31   Modified: 2019-07-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi