An Structural Test Method of Analog Circuits for Improving Test Efficiency of System LSIs
| Project/Area Number |
24700043
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
KOMATSU Satoshi 東京大学, 大規模集積システム設計教育研究センター, 准教授 (90334325)
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| Project Period (FY) |
2012-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2013: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Keywords | ＶＬＳＩ設計技術 / VLSI設計技術 |
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| Research Abstract |
In this study, we have studied on improving test efficiency of system LSIs. To achieve such efficient manufacturing test, we introduced structural test methods which are usually used in testing of digital circuits into testing of analog circuits.
We have evaluated transfer characteristics between input stimulus and output signals by using SPICE simulator. In addition, we also proposed and evaluated on-chip signal sampler circuits which are necessary for on-chip testing of analog circuits. We designed and evaluated analog-to-digital conversion circuits and time-to-digital conversion circuits. The experimental results showed that those circuits can be applied for efficient testing of analog circuits with high precision.
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Report
(3 results)
Research Products
(3 results)
