A general purpose processor based on a multi-valued decision diagram
| Project/Area Number |
24700050
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Ehime University (2014)
Kagoshima University (2012-2013) |
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Principal Investigator |
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2012: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | Decision Diagram / Multi-valued Logic / FPGA / Processor / BDD / MDD / CPU / 組み込みシステム / パケット分類 / 決定グラフ / 組込みプロセッサ / コンパイラ / 多値決定グラフ / プロセッサ / 組込みシステム |
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| Outline of Final Research Achievements |
We proposed the Multi-terminal multiple-valued decision diagram for characteristic function representing cluster decomposition (MTMDD for CF) as a new kind of a decision diagram, then presented at the international conferences. Also, we applied the edge-valued MDD(k), which is a variation of the MTMDD for CF, to realize a new embedded processor. We used it to the multi-core processor to realize the packet classification. Also, we developed the commercial packet classifier with co-development company.
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Report
(4 results)
Research Products
(24 results)
