Transformation from Synchronous Circuits to Low Power Asynchronous Circuits
| Project/Area Number |
24700051
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Aizu |
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Principal Investigator |
SAITO Hiroshi 会津大学, コンピュータ理工学部, 准教授 (50361671)
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | 非同期式回路 / 動作合成 / 低消費電力化 |
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| Outline of Final Research Achievements |
In this research, we proposed a transformation method from structural models of synchronous circuits to the ones of asynchronous circuits with bundled-data implementation. We used a commercial behavioral synthesis tool to generate structural models of synchronous circuits from an application specified by SystemC, a set of resource constraints such as clock cycle time, and a resource library. We developed a tool which is based on the proposed method. As the developed tool generates not only a structural model of a synchronous circuit but also a script used for low level synthesis tools, the design of asynchronous circuits becomes easy using the developed tool.
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Report
(4 results)
Research Products
(8 results)
