| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Outline of Final Research Achievements |
In this research, we proposed a transformation method from structural models of synchronous circuits to the ones of asynchronous circuits with bundled-data implementation. We used a commercial behavioral synthesis tool to generate structural models of synchronous circuits from an application specified by SystemC, a set of resource constraints such as clock cycle time, and a resource library. We developed a tool which is based on the proposed method. As the developed tool generates not only a structural model of a synchronous circuit but also a script used for low level synthesis tools, the design of asynchronous circuits becomes easy using the developed tool.
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