| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Outline of Final Research Achievements |
I developed a power/energy reduction scheme realized by the cooperation between a heterogeneous manycore processor and a parallelizing compilation technique. On a heterogeneous manycore processor, which integrates multiple number/types of processor cores on a chip, it is required to schedule tasks in an parallel application to the cores on a chip considering dependencies among the tasks, characteristics of the cores, and timings to apply DVFS and Power Gating. In this research, an energy efficient task scheduling method for a parallelizing compiler was developed, and it realizes large energy reduction under the cooperation with a heterogeneous manycore architecture.
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