A Power/Energy Reduction Scheme with the Cooperation between a Heterogeneous Multicore Processor and a Parallelizing Compilation Technique
| Project/Area Number |
24700055
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Waseda University (2014)
The University of Electro-Communications (2012-2013) |
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Principal Investigator |
WADA Yasutaka 早稲田大学, 理工学術院, 助教 (40434310)
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | 低消費電力化 / タスクスケジューリング / 自動並列化 / ヘテロジニアスコンピューティング / メニーコア / マルチコア / 並列処理 / 自動並列化コンパイラ / 低消費電力 / アクセラレータ |
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| Outline of Final Research Achievements |
I developed a power/energy reduction scheme realized by the cooperation between a heterogeneous manycore processor and a parallelizing compilation technique. On a heterogeneous manycore processor, which integrates multiple number/types of processor cores on a chip, it is required to schedule tasks in an parallel application to the cores on a chip considering dependencies among the tasks, characteristics of the cores, and timings to apply DVFS and Power Gating. In this research, an energy efficient task scheduling method for a parallelizing compiler was developed, and it realizes large energy reduction under the cooperation with a heterogeneous manycore architecture.
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Report
(4 results)
Research Products
(11 results)
