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Research of BIST for smart analog device

Research Project

Project/Area Number 24860054
Research Category

Grant-in-Aid for Research Activity Start-up

Allocation TypeSingle-year Grants
Research Field Electron device/Electronic equipment
Research InstitutionThe University of Kitakyushu

Principal Investigator

DONG QING  北九州市立大学, 国際環境工学部, 講師 (30638804)

Project Period (FY) 2012-08-31 – 2014-03-31
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
KeywordsアナログLSI / 自己診断システム
Research Abstract

This research introduces a built-in self test(BIST) system , which is a method of Design for Testability for analog LSI test. We explored the analog signal processing and introduced a systematic test method for analog ICs. The developed BIST generates a set of preset analog signals, and input them into each analog device in chip in turn. When a device is activated for inputs, its output signal is also sampled. The sampled signal is then quantized by an ADC, and its amplitude/frequency/phase/delay characteristics are calculated by a digital signal processing unit. These characteristics then are compared with the expected outputs by the control logic unit. The control logic unit finally judges if a circuit failure is determined. The measurement results from the test chip confirmed the testability of the introduced BIST system.

Report

(3 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Annual Research Report
  • Research Products

    (20 results)

All 2013 2012 Other

All Journal Article (4 results) (of which Peer Reviewed: 4 results) Presentation (16 results)

  • [Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013

    • Author(s)
      B. Yang, Q. Dong, J. Li and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A,No.12 Pages: 2475-2486

    • NAID

      130003385300

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Analog circuit synthesis with constraint generation of layout dependent effects by geometric programming2013

    • Author(s)
      Y. Zhang, B. Yang, J. Li, Q. Dong and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A, No.12 Pages: 2487-2498

    • NAID

      130003385301

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013

    • Author(s)
      Bo Yang, Qing Dong, Jing Li and Shigetoshi Nakatake
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E96.A Issue: 12 Pages: 2475-2486

    • DOI

      10.1587/transfun.E96.A.2475

    • NAID

      130003385300

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2013 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming2013

    • Author(s)
      Yu Zhang, Bo Yang, Jing Li, Qing Dong and Shigetoshi Nakatake
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E96.A Issue: 12 Pages: 2487-2498

    • DOI

      10.1587/transfun.E96.A.2487

    • NAID

      130003385301

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2013 Annual Research Report
    • Peer Reviewed
  • [Presentation] Routability-driven Common-centroid Capacitor Array Generation with Signal Coupling Constraints2013

    • Author(s)
      G. Chen, J. Li, B. Yang, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
    • Related Report
      2013 Final Research Report
  • [Presentation] A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements2013

    • Author(s)
      Z. Yu, G. Chen, M. Li, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
    • Related Report
      2013 Final Research Report
  • [Presentation] Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects2013

    • Author(s)
      Y. Zhang, G. Chen, Q. Dong, M. Li and S. Nakatake
    • Organizer
      VLSI-SOC 2013
    • Place of Presentation
      Istanbul, Turkey
    • Year and Date
      2013-10-07
    • Related Report
      2013 Final Research Report
  • [Presentation] Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers2013

    • Author(s)
      M. Li, G. Chen, Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      kws 2013
    • Place of Presentation
      兵庫県淡路市
    • Year and Date
      2013-07-29
    • Related Report
      2013 Final Research Report
  • [Presentation] A 9-bit 50MSps SAR ADC with Pre-charge VCM-based Double Input Range Algorithm2013

    • Author(s)
      G. Chen, Y. Zhang, Q. Dong, B. Yang, J. Li and S. Nakatake
    • Organizer
      GLVLSI 2013
    • Place of Presentation
      Paris, France
    • Year and Date
      2013-05-02
    • Related Report
      2013 Final Research Report
  • [Presentation] A Comparator Energy Model Considering Shallow Trench Isolation Stress by Geometric Programming2013

    • Author(s)
      G. Chen, Y. Zhang, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      ISQED, 2013
    • Place of Presentation
      SantaClara, CA, USA
    • Year and Date
      2013-03-06
    • Related Report
      2013 Final Research Report
  • [Presentation] A Comparator Energy Model Considering Shallow Trench Isolation Stress by Geometric Programming2013

    • Author(s)
      Gong Chen
    • Organizer
      International Symposium on Quality Electronic Design (ISQED)2013
    • Place of Presentation
      SantaClara, CA, USA
    • Related Report
      2012 Annual Research Report
  • [Presentation] High Routability and Low Ratio Mismatch Driven Common-Centroid Capacitor Array Generation2012

    • Author(s)
      J. Li, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08
    • Related Report
      2013 Final Research Report
  • [Presentation] SRAM Macro Synthesis with Layout- dependent Effect by Geometric Programming2012

    • Author(s)
      Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization(VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08
    • Related Report
      2013 Final Research Report
  • [Presentation] High Routability and Low Ratio Mimatch Driven Common-Centroid Capacitor Array Generation2012

    • Author(s)
      Shigetoshi Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization 2012
    • Place of Presentation
      IEEE/ACM Workshop on Variability Modeling and Characterization 2012
    • Related Report
      2012 Annual Research Report
  • [Presentation] SRAM Macro Synthesis with Layout-dependent Effect by Geometric Programming2012

    • Author(s)
      Yu Zhang
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization 2012
    • Place of Presentation
      SanJose, CA, USA
    • Related Report
      2012 Annual Research Report
  • [Presentation] A 9-bit 50MSps SAR ADC with Pre-charge VCM-based Double Input Range Algorithm

    • Author(s)
      Gong Chen
    • Organizer
      GLVLSI 2013
    • Place of Presentation
      Paris, France
    • Related Report
      2013 Annual Research Report
  • [Presentation] Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers,

    • Author(s)
      Mingyu Li
    • Organizer
      kws 2013
    • Place of Presentation
      淡路
    • Related Report
      2013 Annual Research Report
  • [Presentation] Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects,

    • Author(s)
      Yu Zhang
    • Organizer
      VLSI-SOC 2013
    • Place of Presentation
      Istanbul, Turkey
    • Related Report
      2013 Annual Research Report
  • [Presentation] Routability-driven Common-centroid Capacitor Array Generation with Signal Coupling Constraints

    • Author(s)
      Gong Chen
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City, Vietnam
    • Related Report
      2013 Annual Research Report
  • [Presentation] A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements

    • Author(s)
      Zhang Yu
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City, Vietnam
    • Related Report
      2013 Annual Research Report

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Published: 2012-11-27   Modified: 2019-07-29  

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