| Co-Investigator(Kenkyū-buntansha) |
並木 美太郎 東京農工大学, 工学(系)研究科(研究院), 教授 (10208077)
中村 宏 東京大学, 大学院情報理工学系研究科, 教授 (20212102)
宇佐美 公良 芝浦工業大学, 工学部, 教授 (20365547)
近藤 正章 東京大学, 先端科学技術研究センター, その他 (30376660)
黒田 忠広 慶應義塾大学, 理工学部(矢上), 教授 (50327681)
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| Budget Amount *help |
¥216,320,000 (Direct Cost: ¥166,400,000、Indirect Cost: ¥49,920,000)
Fiscal Year 2017: ¥34,840,000 (Direct Cost: ¥26,800,000、Indirect Cost: ¥8,040,000)
Fiscal Year 2016: ¥41,080,000 (Direct Cost: ¥31,600,000、Indirect Cost: ¥9,480,000)
Fiscal Year 2015: ¥35,750,000 (Direct Cost: ¥27,500,000、Indirect Cost: ¥8,250,000)
Fiscal Year 2014: ¥50,180,000 (Direct Cost: ¥38,600,000、Indirect Cost: ¥11,580,000)
Fiscal Year 2013: ¥54,470,000 (Direct Cost: ¥41,900,000、Indirect Cost: ¥12,570,000)
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| Outline of Final Research Achievements |
We established fundamental techniques to build various types of chip combination using inductive coupling through chip interface (TCI). In order to build chips with TCI easily, IPs (Intellectual Properties) from the physical layer to the router layer were developed and openly distributed. Several prototype chips including CPU, accelerators and memory were designed and implemented. Performance and power optimization and adaptation techniques for stacking multiple chips have been investigated. The thermal analysis has been done for chip stack with TCI. The shared buses and point-to-point networks with TCI were investigated. Finally, control software for a system with heterogeneous accelerators were developed.
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