Development of formal design methodology for VLSI datapaths based on Galois-field arithmetic operations
| Project/Area Number |
25240006
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
Homma Naofumi 東北大学, 電気通信研究所, 教授 (00343062)
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| Co-Investigator(Kenkyū-buntansha) |
青木 孝文 東北大学, 情報科学研究科, 教授 (80241529)
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| Project Period (FY) |
2013-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥32,240,000 (Direct Cost: ¥24,800,000、Indirect Cost: ¥7,440,000)
Fiscal Year 2016: ¥7,280,000 (Direct Cost: ¥5,600,000、Indirect Cost: ¥1,680,000)
Fiscal Year 2015: ¥9,360,000 (Direct Cost: ¥7,200,000、Indirect Cost: ¥2,160,000)
Fiscal Year 2014: ¥10,400,000 (Direct Cost: ¥8,000,000、Indirect Cost: ¥2,400,000)
Fiscal Year 2013: ¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
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| Keywords | 計算機システム / LSI設計技術 / ハードウェアセキュリティ / システムオンチップ / VLSI設計技術 / 算術演算回路 / ガロア体 |
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| Outline of Final Research Achievements |
This research project developed a formal design methodology for VLSI datapaths consisting of arithmetic operations on Galois fields. First, we provided (1) a formal description for Galois-field arithmetic circuits based on polynomial basis and normal basis which are frequently used for cryptography and error-correction code, and then developed (2) a formal verification method, which is applicable to the circuit description, using computer algebra. In addition, (3) we applied the design and verification methods to a cryptographic processor. More precisely, we designed a processor datapath for AES, which is one of the ISO/IEC international standard block ciphers, by the developed method. Furthermore, we developed an automatic generator for generating a variety of Galois-field arithmetic circuits depending on various design specification.
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Report
(5 results)
Research Products
(51 results)
