| Budget Amount *help |
¥17,680,000 (Direct Cost: ¥13,600,000、Indirect Cost: ¥4,080,000)
Fiscal Year 2016: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2015: ¥7,150,000 (Direct Cost: ¥5,500,000、Indirect Cost: ¥1,650,000)
Fiscal Year 2014: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2013: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
|
|---|
| Outline of Final Research Achievements |
In this research, we focused on the fact that there are many invalid input transitions that do not contribute to delay fault detection in the LSI scan test, and proposed a selective input transition mask circuit that does not propagate invalid input transitions in the circuit. It was confirmed that the self test power can be drastically reduced without deteriorating the test quality by actual test-chip-based measurement as well as simulatin-based evaluation. Moreover, we succeeded in suppressing the clock stretch and improving the accuracy of the actual speed scan test by reducing the state transition around the clock signal line. The proposed method greatly contributes to the testing of LSI circuits for implantable medical devices that require ultra low power.
|
