Development of a computer system with an efficient core fusion mechanism
Project/Area Number |
25330056
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Research Category |
Grant-in-Aid for Scientific Research (C)
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Allocation Type | Multi-year Fund |
Section | 一般 |
Research Field |
Computer system
|
Research Institution | Tokyo Institute of Technology |
Principal Investigator |
Kise Kenji 東京工業大学, 大学院情報理工学研究科, 准教授 (50323887)
|
Project Period (FY) |
2013-04-01 – 2016-03-31
|
Project Status |
Completed (Fiscal Year 2015)
|
Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2014: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
|
Keywords | コア融合 / 計算機システム / プロセッサ / FPGA |
Outline of Final Research Achievements |
In this research, we designed and verified our realistic microarchitecture of CoreSymphony in hardware description language which enables efficient cooperative core features on multi-core processors. In other words, we reduced the required hardware cost for CoreSymphony processors using sophisticated microarchitecture techniques. Moreover, in order to develop an FPGA (field-programmable gate array) board for computer architecture research, high-speed serial communication between FPGA boards with serial ATA cables is evaluated and confirmed its high data bandwidth and we designed original FPGA board with this high-speed serial communication, FPGA, and DRAM chip.
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Report
(4 results)
Research Products
(7 results)
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[Presentation] The Ultrasmall Soft Processor
Author(s)
Yuichiro Tanaka, Shimpei Sato, Kenji Kise
Organizer
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
Place of Presentation
Edinburgh Scotland
Related Report
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